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i965: Do an end-of-pipe sync after flushes

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According to the docs, a simple CS stall is insufficient to ensure that
the memory from the flush is visible and an end-of-pipe sync is needed.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d9261275cc)
This commit is contained in:
Jason Ekstrand 2017-06-13 10:31:41 -07:00 • committed by Andres Gomez
parent 7d4dcbcad9
commit 175b0442df
1 changed files with 3 additions and 3 deletions
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6
src/mesa/drivers/dri/i965/brw_pipe_control.c
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@ -184,10 +184,10 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
* caches are coherent with memory once the specified R/O caches are
* invalidated. On pre-Gen6 hardware the (implicit) R/O cache
* invalidation seems to happen at the bottom of the pipeline together
* with any write cache flush, so this shouldn't be a concern.
* with any write cache flush, so this shouldn't be a concern. In order
* to ensure a full stall, we do an end-of-pipe sync.
*/
brw_emit_pipe_control_flush(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) |
PIPE_CONTROL_CS_STALL);
brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
}