From 17381f31904d6fea5f237b5638c9e2f068da0f22 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Thu, 2 Jan 2025 10:39:49 -0800 Subject: [PATCH] intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+ Fix invalid SWSB annotation in dEQP-VK.glsl.builtin.precision.mix.mediump.vec4 for LNL. Fixes: 4a24f49b579 ("intel/compiler/xe2: Implement codegen of three-source instructions.") Reviewed-by: Lionel Landwerlin (cherry picked from commit 6968794c504e19a06dcd826afc379c148d22e1fc) Part-of: --- .pick_status.json | 2 +- src/intel/compiler/brw_inst.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 5ef5548dace..a120b8275ee 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -214,7 +214,7 @@ "description": "intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "4a24f49b5790383effadfece49735f27b576de73", "notes": null diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 8409f88257e..b0129b87f30 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -430,7 +430,7 @@ F(3src_no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1) F(3src_no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1) F(3src_mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31) FK(3src_access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) -F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8) +F20(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8) /* Bit 7 is Reserved (for future Opcode expansion) */ F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) /** @} */