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https://gitlab.freedesktop.org/mesa/mesa.git
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radeon: remove unused texmem
This commit is contained in:
Dave Airlie
parent
0a43603c1c
commit
16f4b10170
1 changed files with 0 additions and 404 deletions
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@ -1,404 +0,0 @@
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/**************************************************************************
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Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
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VA Linux Systems Inc., Fremont, California.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation on the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
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SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
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IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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*
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*/
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#include <errno.h>
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#include "main/glheader.h"
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#include "main/imports.h"
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#include "main/context.h"
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#include "main/macros.h"
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#include "radeon_context.h"
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#include "radeon_ioctl.h"
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#include "radeon_tex.h"
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#include <unistd.h> /* for usleep() */
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/**
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* Destroy any device-dependent state associated with the texture. This may
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* include NULLing out hardware state that points to the texture.
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*/
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void
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radeonDestroyTexObj( r100ContextPtr rmesa, radeonTexObjPtr t )
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{
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if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
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fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj );
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}
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if ( rmesa != NULL ) {
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unsigned i;
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for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
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if ( t == rmesa->state.texture.unit[i].texobj ) {
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rmesa->state.texture.unit[i].texobj = NULL;
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}
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}
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}
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}
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/* ------------------------------------------------------------
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* Texture image conversions
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*/
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static void radeonUploadRectSubImage( r100ContextPtr rmesa,
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radeonTexObjPtr t,
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struct gl_texture_image *texImage,
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GLint x, GLint y,
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GLint width, GLint height )
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{
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const struct gl_texture_format *texFormat = texImage->TexFormat;
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int blit_format, dstPitch, done;
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switch ( texFormat->TexelBytes ) {
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case 1:
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blit_format = RADEON_GMC_DST_8BPP_CI;
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break;
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case 2:
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blit_format = RADEON_GMC_DST_16BPP;
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break;
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case 4:
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blit_format = RADEON_GMC_DST_32BPP;
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break;
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default:
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fprintf( stderr, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
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texFormat->TexelBytes);
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return;
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}
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t->image[0][0].data = texImage->Data;
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/* Currently don't need to cope with small pitches.
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*/
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width = texImage->Width;
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height = texImage->Height;
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dstPitch = t->pp_txpitch + 32;
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{ /* FIXME: prefer GART-texturing if possible */
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/* Data not in GART memory, or bad pitch.
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*/
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for (done = 0; done < height ; ) {
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struct radeon_dma_region region;
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int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch );
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int src_pitch;
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char *tex;
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src_pitch = texImage->RowStride * texFormat->TexelBytes;
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tex = (char *)texImage->Data + done * src_pitch;
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memset(®ion, 0, sizeof(region));
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radeonAllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 );
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/* Copy texdata to dma:
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*/
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if (0)
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fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n",
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__FUNCTION__, src_pitch, dstPitch);
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if (src_pitch == dstPitch) {
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memcpy( region.address + region.start, tex, lines * src_pitch );
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}
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else {
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char *buf = region.address + region.start;
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int i;
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for (i = 0 ; i < lines ; i++) {
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memcpy( buf, tex, src_pitch );
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buf += dstPitch;
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tex += src_pitch;
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}
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}
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radeonEmitWait( rmesa, RADEON_WAIT_3D );
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/* Blit to framebuffer
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*/
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radeonEmitBlit( rmesa,
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blit_format,
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dstPitch, GET_START( ®ion ),
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dstPitch, t->bufAddr,
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0, 0,
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0, done,
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width, lines );
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radeonEmitWait( rmesa, RADEON_WAIT_2D );
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radeonReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ );
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done += lines;
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}
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}
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}
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/**
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* Upload the texture image associated with texture \a t at the specified
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* level at the address relative to \a start.
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*/
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static void uploadSubImage( r100ContextPtr rmesa, radeonTexObjPtr t,
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GLint hwlevel,
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GLint x, GLint y, GLint width, GLint height,
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GLuint face )
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{
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struct gl_texture_image *texImage = NULL;
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GLuint offset;
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GLint imageWidth, imageHeight;
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GLint ret;
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drm_radeon_texture_t tex;
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drm_radeon_tex_image_t tmp;
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const int level = hwlevel + t->base.firstLevel;
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if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
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fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
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__FUNCTION__, (void *)t, (void *)t->base.tObj, level, width, height, face );
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}
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ASSERT(face < 6);
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/* Ensure we have a valid texture to upload */
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if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
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_mesa_problem(NULL, "bad texture level in %s", __FUNCTION__);
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return;
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}
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texImage = t->base.tObj->Image[face][level];
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if ( !texImage ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level );
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return;
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}
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if ( !texImage->Data ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
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return;
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}
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if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
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assert(level == 0);
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assert(hwlevel == 0);
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
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radeonUploadRectSubImage( rmesa, t, texImage, x, y, width, height );
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return;
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}
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imageWidth = texImage->Width;
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imageHeight = texImage->Height;
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offset = t->bufAddr + t->base.totalSize * face / 6;
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if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
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GLint imageX = 0;
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GLint imageY = 0;
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GLint blitX = t->image[face][hwlevel].x;
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GLint blitY = t->image[face][hwlevel].y;
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GLint blitWidth = t->image[face][hwlevel].width;
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GLint blitHeight = t->image[face][hwlevel].height;
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fprintf( stderr, " upload image: %d,%d at %d,%d\n",
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imageWidth, imageHeight, imageX, imageY );
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fprintf( stderr, " upload blit: %d,%d at %d,%d\n",
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blitWidth, blitHeight, blitX, blitY );
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fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n",
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(GLuint)offset, hwlevel, level );
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}
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t->image[face][hwlevel].data = texImage->Data;
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/* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
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* NOTE: we're always use a 1KB-wide blit and I8 texture format.
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* We used to use 1, 2 and 4-byte texels and used to use the texture
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* width to dictate the blit width - but that won't work for compressed
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* textures. (Brian)
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* NOTE: can't do that with texture tiling. (sroland)
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*/
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tex.offset = offset;
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tex.image = &tmp;
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/* copy (x,y,width,height,data) */
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memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
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if (texImage->TexFormat->TexelBytes) {
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/* use multi-byte upload scheme */
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tex.height = imageHeight;
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tex.width = imageWidth;
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tex.format = t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK;
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tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
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tex.offset += tmp.x & ~1023;
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tmp.x = tmp.x % 1024;
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if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) {
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/* need something like "tiled coordinates" ? */
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tmp.y = tmp.x / (tex.pitch * 128) * 2;
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tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes;
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tex.pitch |= RADEON_DST_TILE_MICRO >> 22;
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}
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else {
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tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1);
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}
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if ((t->tile_bits & RADEON_TXO_MACRO_TILE) &&
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(texImage->Width * texImage->TexFormat->TexelBytes >= 256)) {
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/* radeon switches off macro tiling for small textures/mipmaps it seems */
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tex.pitch |= RADEON_DST_TILE_MACRO >> 22;
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}
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}
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else {
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/* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
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needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
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/* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
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so the kernel module reads the right amount of data. */
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tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
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tex.pitch = (BLIT_WIDTH_BYTES / 64);
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tex.height = (imageHeight + 3) / 4;
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tex.width = (imageWidth + 3) / 4;
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switch (t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) {
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case RADEON_TXFORMAT_DXT1:
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tex.width *= 8;
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break;
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case RADEON_TXFORMAT_DXT23:
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case RADEON_TXFORMAT_DXT45:
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tex.width *= 16;
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break;
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}
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}
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LOCK_HARDWARE( &rmesa->radeon );
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do {
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ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
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&tex, sizeof(drm_radeon_texture_t) );
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} while ( ret == -EAGAIN );
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UNLOCK_HARDWARE( &rmesa->radeon );
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if ( ret ) {
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fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
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fprintf( stderr, " offset=0x%08x\n",
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offset );
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fprintf( stderr, " image width=%d height=%d\n",
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imageWidth, imageHeight );
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fprintf( stderr, " blit width=%d height=%d data=%p\n",
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t->image[face][hwlevel].width, t->image[face][hwlevel].height,
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t->image[face][hwlevel].data );
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exit( 1 );
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}
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}
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/**
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* Upload the texture images associated with texture \a t. This might
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* require the allocation of texture memory.
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*
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* \param rmesa Context pointer
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* \param t Texture to be uploaded
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* \param face Cube map face to be uploaded. Zero for non-cube maps.
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*/
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int radeonUploadTexImages( r100ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
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{
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int numLevels;
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if ( !t || t->base.totalSize == 0 || t->image_override )
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return 0;
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if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
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fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
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(void *)rmesa->radeon.glCtx, (void *)t->base.tObj, t->base.totalSize,
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t->base.firstLevel, t->base.lastLevel );
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}
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numLevels = t->base.lastLevel - t->base.firstLevel + 1;
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if (RADEON_DEBUG & DEBUG_SYNC) {
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fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
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radeonFinish( rmesa->radeon.glCtx );
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}
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LOCK_HARDWARE( &rmesa->radeon );
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if ( t->base.memBlock == NULL ) {
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int heap;
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heap = driAllocateTexture( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
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(driTextureObject *) t );
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if ( heap == -1 ) {
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UNLOCK_HARDWARE( &rmesa->radeon );
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return -1;
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}
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/* Set the base offset of the texture image */
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t->bufAddr = rmesa->radeon.radeonScreen->texOffset[heap]
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+ t->base.memBlock->ofs;
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t->pp_txoffset = t->bufAddr;
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if (!(t->base.tObj->Image[0][0]->IsClientData)) {
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/* hope it's safe to add that here... */
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t->pp_txoffset |= t->tile_bits;
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}
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/* Mark this texobj as dirty on all units:
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*/
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t->dirty_state = R100_TEX_ALL;
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}
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/* Let the world know we've used this memory recently.
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*/
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driUpdateTextureLRU( (driTextureObject *) t );
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UNLOCK_HARDWARE( &rmesa->radeon );
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/* Upload any images that are new */
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if (t->base.dirty_images[face]) {
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int i;
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for ( i = 0 ; i < numLevels ; i++ ) {
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if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) {
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uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width,
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t->image[face][i].height, face );
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}
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}
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t->base.dirty_images[face] = 0;
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}
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if (RADEON_DEBUG & DEBUG_SYNC) {
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fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
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radeonFinish( rmesa->radeon.glCtx );
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}
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return 0;
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}
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