diff --git a/.pick_status.json b/.pick_status.json
index e1ee2ca85ab..aa675b9ca6c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -674,7 +674,7 @@
         "description": "ac,radv,radeonsi: fix programming PA_SU_PRIM_FILTER_CNTL on GFX12",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c
index 57d5ae1cfa5..cd23a1f9ce3 100644
--- a/src/amd/common/ac_cmdbuf.c
+++ b/src/amd/common/ac_cmdbuf.c
@@ -743,6 +743,12 @@ gfx12_init_graphics_preamble_state(const struct ac_preamble_state *state,
    ac_pm4_set_reg(pm4, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 0);
    ac_pm4_set_reg(pm4, R_030A04_PA_SC_LINE_STIPPLE_STATE, 0);
 
+   /* On GFX12, this seems to behave slightly differently. Programming the
+    * EXCLUSION fields to TRUE causes zero-area triangles to not pass the
+    * primitive clipping stage.
+    */
+   ac_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
+
    ac_pm4_set_reg(pm4, R_031128_SPI_GRP_LAUNCH_GUARANTEE_ENABLE,
                   S_031128_ENABLE(1) |
                   S_031128_GS_ASSIST_EN(1) |
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a8d2269a202..2fba3345420 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1264,7 +1264,7 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
    radeon_emit(centroid_priority);
    radeon_emit(centroid_priority >> 32);
 
-   if (pdev->info.gfx_level >= GFX7) {
+   if (pdev->info.gfx_level >= GFX7 && pdev->info.gfx_level < GFX12) {
       /* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the pixel boundary
        * (-8 sample offset).
        */
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4d6ba6ae3aa..92f045367cf 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1014,7 +1014,7 @@ radv_emit_default_sample_locations(const struct radv_physical_device *pdev, stru
     * pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't
     * support 16 samples.
     */
-   if (pdev->info.gfx_level >= GFX7) {
+   if (pdev->info.gfx_level >= GFX7 && pdev->info.gfx_level < GFX12) {
       radeon_set_context_reg(R_02882C_PA_SU_PRIM_FILTER_CNTL,
                              S_02882C_XMAX_RIGHT_EXCLUSION(1) | S_02882C_YMAX_BOTTOM_EXCLUSION(1));
    }
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8061be47aa7..d122400c0c7 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4985,7 +4985,7 @@ static void si_init_graphics_preamble_state(struct si_context *sctx,
 
    ac_init_graphics_preamble_state(&preamble_state, &pm4->base);
 
-   if (sctx->gfx_level >= GFX7) {
+   if (sctx->gfx_level >= GFX7 && sctx->gfx_level < GFX12) {
       /* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
       ac_pm4_set_reg(&pm4->base, R_02882C_PA_SU_PRIM_FILTER_CNTL,
                      S_02882C_XMAX_RIGHT_EXCLUSION(1) |