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aco: Implement b2b32 and b2b1

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The implementations here just clone i2b32 and i2b1.  This means that
b2b32 doesn't technically generate true NIR 0/-1 booleans but it should
be fine as it's only ever generated for shared variable writes which
will always be consumed by something which will then run it through an
i2b again.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
This commit is contained in:
Jason Ekstrand 2020-03-27 11:49:14 -05:00 • committed by Marge Bot
parent b2db84153a
commit 16a80ff18a
2 changed files with 4 additions and 0 deletions
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2
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -2247,6 +2247,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_b2b32:
case nir_op_b2i32: {
Temp src = get_alu_src(ctx, instr->src[0]);
assert(src.regClass() == bld.lm);
@ -2261,6 +2262,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_b2b1:
case nir_op_i2b1: {
Temp src = get_alu_src(ctx, instr->src[0]);
assert(dst.regClass() == bld.lm);

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -323,11 +323,13 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_op_ieq:
case nir_op_ine:
case nir_op_i2b1:
case nir_op_b2b1:
size = lane_mask_size;
break;
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_b2i32:
case nir_op_b2b32:
case nir_op_b2f32:
case nir_op_f2i32:
case nir_op_f2u32: