mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-04-19 10:10:39 +02:00
aco: Don't allow any VALU instruction to write m0.
Fixes: d5398b62da
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22885>
This commit is contained in:
parent
c140a456b7
commit
16a05f1903
3 changed files with 7 additions and 6 deletions
|
|
@ -480,22 +480,23 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx)
|
|||
}
|
||||
|
||||
bool
|
||||
can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr)
|
||||
can_write_m0(const aco_ptr<Instruction>& instr)
|
||||
{
|
||||
if (instr->isSALU())
|
||||
return true;
|
||||
|
||||
/* VALU can't write m0 on any GPU generations. */
|
||||
if (instr->isVALU())
|
||||
return gfx_level >= GFX9;
|
||||
return false;
|
||||
|
||||
switch (instr->opcode) {
|
||||
case aco_opcode::p_parallelcopy:
|
||||
case aco_opcode::p_extract:
|
||||
case aco_opcode::p_insert:
|
||||
/* These pseudo instructions are implemented with SALU when writing m0. */
|
||||
return true;
|
||||
case aco_opcode::p_reload:
|
||||
return gfx_level >= GFX9;
|
||||
default:
|
||||
/* Assume that no other instructions can write m0. */
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1804,7 +1804,7 @@ bool instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op);
|
|||
uint8_t get_gfx11_true16_mask(aco_opcode op);
|
||||
bool can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra);
|
||||
bool can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8);
|
||||
bool can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr);
|
||||
bool can_write_m0(const aco_ptr<Instruction>& instr);
|
||||
/* updates "instr" and returns the old instruction (or NULL if no update was needed) */
|
||||
aco_ptr<Instruction> convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr);
|
||||
aco_ptr<Instruction> convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8);
|
||||
|
|
|
|||
|
|
@ -1656,7 +1656,7 @@ get_reg(ra_ctx& ctx, RegisterFile& reg_file, Temp temp,
|
|||
}
|
||||
if (ctx.assignments[temp.id()].m0) {
|
||||
if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, m0) &&
|
||||
can_write_m0(ctx.program->gfx_level, instr))
|
||||
can_write_m0(instr))
|
||||
return m0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue