fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 09:28:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

gallium: Use explicit values in caps enums.

Browse source 
Simplifies mapping between numbers and identifiers for these.
This commit is contained in:
Michel Dänzer 2011-03-30 10:20:00 +02:00
parent 72e82418ef
commit 167d35c303
1 changed files with 63 additions and 63 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

126
src/gallium/include/pipe/p_defines.h
View file

@ -414,79 +414,79 @@ enum pipe_transfer_usage {
* pipe_screen::get_param() and pipe_screen::get_paramf().
*/
enum pipe_cap {
PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS,
PIPE_CAP_NPOT_TEXTURES,
PIPE_CAP_TWO_SIDED_STENCIL,
PIPE_CAP_GLSL, /* XXX need something better */
PIPE_CAP_DUAL_SOURCE_BLEND,
PIPE_CAP_ANISOTROPIC_FILTER,
PIPE_CAP_POINT_SPRITE,
PIPE_CAP_MAX_RENDER_TARGETS,
PIPE_CAP_OCCLUSION_QUERY,
PIPE_CAP_TIMER_QUERY,
PIPE_CAP_TEXTURE_SHADOW_MAP,
PIPE_CAP_TEXTURE_SWIZZLE,
PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
PIPE_CAP_MAX_LINE_WIDTH,
PIPE_CAP_MAX_LINE_WIDTH_AA,
PIPE_CAP_MAX_POINT_WIDTH,
PIPE_CAP_MAX_POINT_WIDTH_AA,
PIPE_CAP_MAX_TEXTURE_ANISOTROPY,
PIPE_CAP_MAX_TEXTURE_LOD_BIAS,
PIPE_CAP_GUARD_BAND_LEFT, /*< float */
PIPE_CAP_GUARD_BAND_TOP, /*< float */
PIPE_CAP_GUARD_BAND_RIGHT, /*< float */
PIPE_CAP_GUARD_BAND_BOTTOM, /*< float */
PIPE_CAP_TEXTURE_MIRROR_CLAMP,
PIPE_CAP_TEXTURE_MIRROR_REPEAT,
PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS,
PIPE_CAP_BLEND_EQUATION_SEPARATE,
PIPE_CAP_SM3, /*< Shader Model, supported */
PIPE_CAP_STREAM_OUTPUT,
PIPE_CAP_PRIMITIVE_RESTART,
PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS = 0,
PIPE_CAP_NPOT_TEXTURES = 1,
PIPE_CAP_TWO_SIDED_STENCIL = 2,
PIPE_CAP_GLSL = 3, /* XXX need something better */
PIPE_CAP_DUAL_SOURCE_BLEND = 4,
PIPE_CAP_ANISOTROPIC_FILTER = 5,
PIPE_CAP_POINT_SPRITE = 6,
PIPE_CAP_MAX_RENDER_TARGETS = 7,
PIPE_CAP_OCCLUSION_QUERY = 8,
PIPE_CAP_TIMER_QUERY = 9,
PIPE_CAP_TEXTURE_SHADOW_MAP = 10,
PIPE_CAP_TEXTURE_SWIZZLE = 11,
PIPE_CAP_MAX_TEXTURE_2D_LEVELS = 12,
PIPE_CAP_MAX_TEXTURE_3D_LEVELS = 13,
PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS = 14,
PIPE_CAP_MAX_LINE_WIDTH = 15,
PIPE_CAP_MAX_LINE_WIDTH_AA = 16,
PIPE_CAP_MAX_POINT_WIDTH = 17,
PIPE_CAP_MAX_POINT_WIDTH_AA = 18,
PIPE_CAP_MAX_TEXTURE_ANISOTROPY = 19,
PIPE_CAP_MAX_TEXTURE_LOD_BIAS = 20,
PIPE_CAP_GUARD_BAND_LEFT = 21, /*< float */
PIPE_CAP_GUARD_BAND_TOP = 22, /*< float */
PIPE_CAP_GUARD_BAND_RIGHT = 23, /*< float */
PIPE_CAP_GUARD_BAND_BOTTOM = 24, /*< float */
PIPE_CAP_TEXTURE_MIRROR_CLAMP = 25,
PIPE_CAP_TEXTURE_MIRROR_REPEAT = 26,
PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS = 27,
PIPE_CAP_BLEND_EQUATION_SEPARATE = 28,
PIPE_CAP_SM3 = 29, /*< Shader Model, supported */
PIPE_CAP_STREAM_OUTPUT = 30,
PIPE_CAP_PRIMITIVE_RESTART = 31,
/** Maximum texture image units accessible from vertex and fragment shaders
* combined */
PIPE_CAP_MAX_COMBINED_SAMPLERS,
PIPE_CAP_MAX_COMBINED_SAMPLERS = 32,
/** blend enables and write masks per rendertarget */
PIPE_CAP_INDEP_BLEND_ENABLE,
PIPE_CAP_INDEP_BLEND_ENABLE = 33,
/** different blend funcs per rendertarget */
PIPE_CAP_INDEP_BLEND_FUNC,
PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE,
PIPE_CAP_ARRAY_TEXTURES,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
PIPE_CAP_DEPTH_CLAMP,
PIPE_CAP_SHADER_STENCIL_EXPORT,
PIPE_CAP_TGSI_INSTANCEID,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL
PIPE_CAP_INDEP_BLEND_FUNC = 34,
PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE = 35,
PIPE_CAP_ARRAY_TEXTURES = 36,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT = 37,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT = 38,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER = 39,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER = 40,
PIPE_CAP_DEPTH_CLAMP = 41,
PIPE_CAP_SHADER_STENCIL_EXPORT = 42,
PIPE_CAP_TGSI_INSTANCEID = 43,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR = 44,
PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL = 45,
};
/* Shader caps not specific to any single stage */
enum pipe_shader_cap
{
PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
PIPE_SHADER_CAP_MAX_INPUTS,
PIPE_SHADER_CAP_MAX_CONSTS,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
PIPE_SHADER_CAP_MAX_TEMPS,
PIPE_SHADER_CAP_MAX_ADDRS,
PIPE_SHADER_CAP_MAX_PREDS,
PIPE_SHADER_CAP_MAX_INSTRUCTIONS = 0, /* if 0, it means the stage is unsupported */
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS = 1,
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS = 2,
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS = 3,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH = 4,
PIPE_SHADER_CAP_MAX_INPUTS = 5,
PIPE_SHADER_CAP_MAX_CONSTS = 6,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS = 7,
PIPE_SHADER_CAP_MAX_TEMPS = 8,
PIPE_SHADER_CAP_MAX_ADDRS = 9,
PIPE_SHADER_CAP_MAX_PREDS = 10,
/* boolean caps */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 11,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR = 12,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR = 13,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR = 14,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR = 15,
PIPE_SHADER_CAP_SUBROUTINES = 16, /* BGNSUB, ENDSUB, CAL, RET */
};