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radv: Fix exporting/importing multisample images.
Otherwise FMASK metadata segfaults and on import we disable it ... CC: mesa-stable Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7358>
This commit is contained in:
Bas Nieuwenhuizen
Marge Bot
parent
fb1793bf9c
commit
1675c83a4f
2 changed files with 128 additions and 123 deletions
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@ -5266,7 +5266,8 @@ static VkResult radv_alloc_memory(struct radv_device *device,
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}
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if (mem->image && mem->image->plane_count == 1 &&
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!vk_format_is_depth_or_stencil(mem->image->vk_format)) {
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!vk_format_is_depth_or_stencil(mem->image->vk_format) &&
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mem->image->info.samples == 1) {
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struct radeon_bo_metadata metadata;
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device->ws->buffer_get_metadata(mem->bo, &metadata);
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@ -854,49 +854,51 @@ gfx10_make_texture_descriptor(struct radv_device *device,
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}
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/* Initialize the sampler view for FMASK. */
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if (radv_image_has_fmask(image)) {
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uint64_t gpu_address = radv_buffer_get_va(image->bo);
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uint32_t format;
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uint64_t va;
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if (fmask_state) {
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if (radv_image_has_fmask(image)) {
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uint64_t gpu_address = radv_buffer_get_va(image->bo);
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uint32_t format;
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uint64_t va;
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assert(image->plane_count == 1);
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assert(image->plane_count == 1);
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va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
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va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
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switch (image->info.samples) {
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case 2:
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format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
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break;
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case 4:
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format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
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break;
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case 8:
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format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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switch (image->info.samples) {
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case 2:
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format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
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break;
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case 4:
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format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
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break;
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case 8:
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format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
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fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
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S_00A004_FORMAT(format) |
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S_00A004_WIDTH_LO(width - 1);
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fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
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S_00A008_HEIGHT(height - 1) |
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S_00A008_RESOURCE_LEVEL(1);
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fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
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S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
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fmask_state[4] = S_00A010_DEPTH(last_layer) |
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S_00A010_BASE_ARRAY(first_layer);
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fmask_state[5] = 0;
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fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
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fmask_state[7] = 0;
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} else if (fmask_state)
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memset(fmask_state, 0, 8 * 4);
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fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
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fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
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S_00A004_FORMAT(format) |
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S_00A004_WIDTH_LO(width - 1);
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fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
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S_00A008_HEIGHT(height - 1) |
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S_00A008_RESOURCE_LEVEL(1);
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fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
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S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
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fmask_state[4] = S_00A010_DEPTH(last_layer) |
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S_00A010_BASE_ARRAY(first_layer);
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fmask_state[5] = 0;
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fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
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fmask_state[7] = 0;
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} else
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memset(fmask_state, 0, 8 * 4);
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}
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}
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/**
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@ -1018,94 +1020,96 @@ si_make_texture_descriptor(struct radv_device *device,
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}
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/* Initialize the sampler view for FMASK. */
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if (radv_image_has_fmask(image)) {
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uint32_t fmask_format, num_format;
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uint64_t gpu_address = radv_buffer_get_va(image->bo);
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uint64_t va;
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if (fmask_state) {
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if (radv_image_has_fmask(image)) {
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uint32_t fmask_format, num_format;
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uint64_t gpu_address = radv_buffer_get_va(image->bo);
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uint64_t va;
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assert(image->plane_count == 1);
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assert(image->plane_count == 1);
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va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
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va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
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if (device->physical_device->rad_info.chip_class == GFX9) {
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
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switch (image->info.samples) {
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case 2:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
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break;
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case 4:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
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break;
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case 8:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
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break;
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default:
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unreachable("invalid nr_samples");
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if (device->physical_device->rad_info.chip_class == GFX9) {
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
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switch (image->info.samples) {
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case 2:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
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break;
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case 4:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
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break;
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case 8:
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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} else {
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switch (image->info.samples) {
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case 2:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
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break;
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case 4:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
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break;
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case 8:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
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break;
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default:
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assert(0);
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fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
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}
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num_format = V_008F14_IMG_NUM_FORMAT_UINT;
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}
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} else {
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switch (image->info.samples) {
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case 2:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
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break;
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case 4:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
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break;
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case 8:
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fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
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break;
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default:
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assert(0);
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fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
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fmask_state[0] = va >> 8;
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fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
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fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
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S_008F14_DATA_FORMAT(fmask_format) |
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S_008F14_NUM_FORMAT(num_format);
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fmask_state[2] = S_008F18_WIDTH(width - 1) |
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S_008F18_HEIGHT(height - 1);
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fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
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fmask_state[4] = 0;
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fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
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fmask_state[6] = 0;
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fmask_state[7] = 0;
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if (device->physical_device->rad_info.chip_class == GFX9) {
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fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
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fmask_state[4] |= S_008F20_DEPTH(last_layer) |
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S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
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fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
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S_008F24_META_RB_ALIGNED(1);
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if (radv_image_is_tc_compat_cmask(image)) {
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va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
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fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
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fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
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fmask_state[7] |= va >> 8;
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}
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} else {
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fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
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fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
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S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
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fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
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if (radv_image_is_tc_compat_cmask(image)) {
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va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
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fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
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fmask_state[7] |= va >> 8;
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}
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}
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num_format = V_008F14_IMG_NUM_FORMAT_UINT;
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}
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fmask_state[0] = va >> 8;
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fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
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fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
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S_008F14_DATA_FORMAT(fmask_format) |
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S_008F14_NUM_FORMAT(num_format);
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fmask_state[2] = S_008F18_WIDTH(width - 1) |
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S_008F18_HEIGHT(height - 1);
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fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
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fmask_state[4] = 0;
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fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
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fmask_state[6] = 0;
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fmask_state[7] = 0;
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if (device->physical_device->rad_info.chip_class == GFX9) {
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fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
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fmask_state[4] |= S_008F20_DEPTH(last_layer) |
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S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
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fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
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S_008F24_META_RB_ALIGNED(1);
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if (radv_image_is_tc_compat_cmask(image)) {
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va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
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fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
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fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
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fmask_state[7] |= va >> 8;
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}
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} else {
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fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
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fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
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S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
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fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
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if (radv_image_is_tc_compat_cmask(image)) {
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va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
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fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
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fmask_state[7] |= va >> 8;
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}
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}
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} else if (fmask_state)
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memset(fmask_state, 0, 8 * 4);
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} else
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memset(fmask_state, 0, 8 * 4);
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}
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}
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static void
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