From 165a0105d3dec1aca3d51c49d76a9c8a4f09553c Mon Sep 17 00:00:00 2001 From: David Rosca Date: Thu, 21 May 2026 14:28:27 +0200 Subject: [PATCH] ac/vcn_dec: Move register defines to ac_vcn_dec.c Also remove unused struct jpeg_params. Reviewed-by: Samuel Pitoiset Reviewed-by: Benjamin Cheng Part-of: --- src/amd/common/ac_vcn_dec.c | 21 +++++++++++++++++++++ src/amd/common/ac_vcn_dec.h | 36 ------------------------------------ 2 files changed, 21 insertions(+), 36 deletions(-) diff --git a/src/amd/common/ac_vcn_dec.c b/src/amd/common/ac_vcn_dec.c index 50dd3bd6b04..1858ccc4850 100644 --- a/src/amd/common/ac_vcn_dec.c +++ b/src/amd/common/ac_vcn_dec.c @@ -23,6 +23,27 @@ #define CMAC_SIZE AES_BLOCK_SIZE #define MAX_SUBSAMPLES 288 /* Maximum subsamples in a sample */ +#define RDECODE_VCN1_GPCOM_VCPU_CMD 0x2070c +#define RDECODE_VCN1_GPCOM_VCPU_DATA0 0x20710 +#define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714 +#define RDECODE_VCN1_ENGINE_CNTL 0x20718 + +#define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2) +#define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2) +#define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2) +#define RDECODE_VCN2_GPCOM_VCPU_DATA2 (0x54C << 2) +#define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2) + +#define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c +#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40 +#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44 +#define RDECODE_VCN2_5_GPCOM_VCPU_DATA2 0x1A0 +#define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4 + +#define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024) +#define RDECODE_MAX_SUBSAMPLE_SIZE (2048 * 2 * 4) +#define RDECODE_IT_SCALING_TABLE_SIZE 992 + typedef struct PACKED _secure_buffer_header { uint8_t cookie[8]; /* 8-byte cookie with value 'wvcencsb' */ diff --git a/src/amd/common/ac_vcn_dec.h b/src/amd/common/ac_vcn_dec.h index 7f96924bff0..6a40403dd1a 100644 --- a/src/amd/common/ac_vcn_dec.h +++ b/src/amd/common/ac_vcn_dec.h @@ -1244,21 +1244,6 @@ typedef struct rvcn_dec_av1_segment_fg_s { rvcn_dec_av1_fg_init_buf_t fg_buf; } rvcn_dec_av1_segment_fg_t; -struct jpeg_params { - unsigned bsd_size; - unsigned dt_pitch; - unsigned dt_uv_pitch; - unsigned dt_luma_top_offset; - unsigned dt_chroma_top_offset; - unsigned dt_chromav_top_offset; - unsigned dt_addr_mode; - unsigned dt_swizzle_mode; - uint16_t crop_x; - uint16_t crop_y; - uint16_t crop_width; - uint16_t crop_height; -}; - struct ac_vcn_dec_reg { uint32_t data0; uint32_t data1; @@ -1267,27 +1252,6 @@ struct ac_vcn_dec_reg { uint32_t cntl; }; -#define RDECODE_VCN1_GPCOM_VCPU_CMD 0x2070c -#define RDECODE_VCN1_GPCOM_VCPU_DATA0 0x20710 -#define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714 -#define RDECODE_VCN1_ENGINE_CNTL 0x20718 - -#define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2) -#define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2) -#define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2) -#define RDECODE_VCN2_GPCOM_VCPU_DATA2 (0x54C << 2) -#define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2) - -#define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c -#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40 -#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44 -#define RDECODE_VCN2_5_GPCOM_VCPU_DATA2 0x1A0 -#define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4 - -#define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024) -#define RDECODE_MAX_SUBSAMPLE_SIZE (2048 * 2 * 4) -#define RDECODE_IT_SCALING_TABLE_SIZE 992 - void ac_vcn_dec_init_regs(struct ac_vcn_dec_reg *reg, enum vcn_version version); uint32_t ac_vcn_dec_dpb_size(const struct radeon_info *info, struct ac_video_dec_session_param *param);