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r300/compiler: Implement the texture semaphore
The texture semaphore allows for prefetching of texture data. On my RV515, this increases the FPS of Lightsmark by 33% (This is with the reg_rename pass enabled, which is enabled in the next commit). There is a new env variable now called RADEON_TEX_GROUP, which allows you to specify the maximum number of texture lookups to do at once. The default is 8, but different values could produce better results for various application / card combinations.
This commit is contained in:
Tom Stellard
parent
51fe9994bd
commit
163629fd05
6 changed files with 308 additions and 49 deletions
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@ -262,7 +262,7 @@ static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair
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} else {
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code->inst[ip].inst0 = R500_INST_TYPE_ALU;
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}
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code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
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code->inst[ip].inst0 |= (inst->SemWait << R500_INST_TEX_SEM_WAIT_SHIFT);
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code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11);
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code->inst[ip].inst0 |= inst->Alpha.WriteMask ? 1 << 14 : 0;
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@ -380,9 +380,9 @@ static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_inst
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code->inst[ip].inst0 = R500_INST_TYPE_TEX
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| (inst->DstReg.WriteMask << 11)
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| R500_INST_TEX_SEM_WAIT;
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| (inst->TexSemWait << R500_INST_TEX_SEM_WAIT_SHIFT);
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code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit)
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| R500_TEX_SEM_ACQUIRE;
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| (inst->TexSemAcquire << R500_TEX_SEM_ACQUIRE_SHIFT);
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if (inst->TexSrcTarget == RC_TEXTURE_RECT)
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code->inst[ip].inst1 |= R500_TEX_UNSCALED;
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@ -650,6 +650,9 @@ void r500BuildFragmentProgramHwCode(struct radeon_compiler *c, void *user)
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}
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}
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/* Make sure TEX_SEM_WAIT is set on the last instruction */
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code->inst[code->inst_end].inst0 |= R500_INST_TEX_SEM_WAIT;
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if (code->max_temp_idx >= compiler->Base.max_temp_regs)
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rc_error(&compiler->Base, "Too many hardware temporaries used");
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@ -32,7 +32,10 @@
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#include "radeon_compiler.h"
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#include "radeon_compiler_util.h"
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#include "radeon_dataflow.h"
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#include "radeon_list.h"
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#include "radeon_variable.h"
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#include "util/u_debug.h"
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#define VERBOSE 0
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@ -65,6 +68,17 @@ struct schedule_instruction {
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* PairedInst references the alpha insturction's dependency information.
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*/
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struct schedule_instruction * PairedInst;
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/** This scheduler uses the value of Score to determine which
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* instruction to schedule. Instructions with a higher value of Score
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* will be scheduled first. */
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int Score;
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/** The number of components that read from a TEX instruction. */
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unsigned TexReadCount;
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/** For TEX instructions a list of readers */
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struct rc_list * TexReaders;
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};
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@ -131,6 +145,12 @@ struct schedule_state {
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struct schedule_instruction *ReadyAlpha;
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struct schedule_instruction *ReadyTEX;
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/*@}*/
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struct rc_list *PendingTEX;
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void (*CalcScore)(struct schedule_instruction *);
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long max_tex_group;
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unsigned PrevBlockHasTex:1;
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unsigned TEXCount;
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};
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static struct reg_value ** get_reg_valuep(struct schedule_state * s,
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@ -147,6 +167,29 @@ static struct reg_value ** get_reg_valuep(struct schedule_state * s,
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return &s->Temporary[index].Values[chan];
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}
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static unsigned get_tex_read_count(struct schedule_instruction * sinst)
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{
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unsigned tex_read_count = sinst->TexReadCount;
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if (sinst->PairedInst) {
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tex_read_count += sinst->PairedInst->TexReadCount;
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}
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return tex_read_count;
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}
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#if VERBOSE
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static void print_list(struct schedule_instruction * sinst)
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{
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struct schedule_instruction * ptr;
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for (ptr = sinst; ptr; ptr=ptr->NextReady) {
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unsigned tex_read_count = get_tex_read_count(ptr);
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unsigned score = sinst->Score;
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fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score,
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tex_read_count);
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}
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fprintf(stderr, "\n");
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}
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#endif
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static void remove_inst_from_list(struct schedule_instruction ** list,
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struct schedule_instruction * inst)
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{
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@ -172,17 +215,28 @@ static void add_inst_to_list(struct schedule_instruction ** list, struct schedul
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*list = inst;
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}
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static void add_inst_to_list_end(struct schedule_instruction ** list,
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static void add_inst_to_list_score(struct schedule_instruction ** list,
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struct schedule_instruction * inst)
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{
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if(!*list){
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struct schedule_instruction * temp;
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struct schedule_instruction * prev;
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if (!*list) {
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*list = inst;
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}else{
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struct schedule_instruction * temp = *list;
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while(temp->NextReady){
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temp = temp->NextReady;
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}
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temp->NextReady = inst;
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return;
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}
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temp = *list;
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prev = NULL;
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while(temp && inst->Score <= temp->Score) {
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prev = temp;
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temp = temp->NextReady;
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}
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if (!prev) {
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inst->NextReady = temp;
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*list = inst;
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} else {
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prev->NextReady = inst;
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inst->NextReady = temp;
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}
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}
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@ -193,13 +247,13 @@ static void instruction_ready(struct schedule_state * s, struct schedule_instruc
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/* Adding Ready TEX instructions to the end of the "Ready List" helps
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* us emit TEX instructions in blocks without losing our place. */
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if (sinst->Instruction->Type == RC_INSTRUCTION_NORMAL)
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add_inst_to_list_end(&s->ReadyTEX, sinst);
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add_inst_to_list_score(&s->ReadyTEX, sinst);
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else if (sinst->Instruction->U.P.Alpha.Opcode == RC_OPCODE_NOP)
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add_inst_to_list(&s->ReadyRGB, sinst);
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add_inst_to_list_score(&s->ReadyRGB, sinst);
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else if (sinst->Instruction->U.P.RGB.Opcode == RC_OPCODE_NOP)
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add_inst_to_list(&s->ReadyAlpha, sinst);
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add_inst_to_list_score(&s->ReadyAlpha, sinst);
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else
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add_inst_to_list(&s->ReadyFullALU, sinst);
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add_inst_to_list_score(&s->ReadyFullALU, sinst);
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}
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static void decrease_dependencies(struct schedule_state * s, struct schedule_instruction * sinst)
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@ -210,6 +264,68 @@ static void decrease_dependencies(struct schedule_state * s, struct schedule_ins
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instruction_ready(s, sinst);
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}
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/* These functions provide different heuristics for scheduling instructions.
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* The default is calc_score_readers. */
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#if 0
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static void calc_score_zero(struct schedule_instruction * sinst)
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{
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sinst->Score = 0;
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}
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static void calc_score_deps(struct schedule_instruction * sinst)
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{
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int i;
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sinst->Score = 0;
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for (i = 0; i < sinst->NumWriteValues; i++) {
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struct reg_value * v = sinst->WriteValues[i];
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if (v->NumReaders) {
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struct reg_value_reader * r;
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for (r = v->Readers; r; r = r->Next) {
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if (r->Reader->NumDependencies == 1) {
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sinst->Score += 100;
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}
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sinst->Score += r->Reader->NumDependencies;
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}
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}
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}
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}
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#endif
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#define NO_READ_TEX_SCORE (1 << 16)
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#define NO_OUTPUT_SCORE (1 << 24)
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static void calc_score_readers(struct schedule_instruction * sinst)
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{
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if (sinst->Instruction->Type == RC_INSTRUCTION_NORMAL) {
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sinst->Score = 0;
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} else {
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sinst->Score = sinst->NumReadValues;
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if (sinst->PairedInst) {
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sinst->Score += sinst->PairedInst->NumReadValues;
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}
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if (get_tex_read_count(sinst) == 0) {
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sinst->Score |= NO_READ_TEX_SCORE;
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}
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if (!sinst->Instruction->U.P.RGB.OutputWriteMask &&
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!sinst->Instruction->U.P.Alpha.OutputWriteMask) {
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if (sinst->PairedInst) {
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if (!sinst->PairedInst->Instruction->U.P.
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RGB.OutputWriteMask
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&& !sinst->PairedInst->Instruction->U.P.
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Alpha.OutputWriteMask) {
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sinst->Score |= NO_OUTPUT_SCORE;
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}
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} else {
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sinst->Score |= NO_OUTPUT_SCORE;
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}
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}
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}
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}
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/**
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* This function decreases the dependencies of the next instruction that
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* wants to write to each of sinst's read values.
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@ -222,8 +338,9 @@ static void commit_update_reads(struct schedule_state * s,
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assert(v->NumReaders > 0);
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v->NumReaders--;
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if (!v->NumReaders) {
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if (v->Next)
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if (v->Next) {
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decrease_dependencies(s, v->Next->Writer);
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}
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}
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}
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if (sinst->PairedInst) {
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@ -256,13 +373,33 @@ static void commit_update_writes(struct schedule_state * s,
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}
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}
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static void notify_sem_wait(struct schedule_state *s)
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{
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struct rc_list * pend_ptr;
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for (pend_ptr = s->PendingTEX; pend_ptr; pend_ptr = pend_ptr->Next) {
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struct rc_list * read_ptr;
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struct schedule_instruction * pending = pend_ptr->Item;
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for (read_ptr = pending->TexReaders; read_ptr;
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read_ptr = read_ptr->Next) {
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struct schedule_instruction * reader = read_ptr->Item;
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reader->TexReadCount--;
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}
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}
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s->PendingTEX = NULL;
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}
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static void commit_alu_instruction(struct schedule_state * s, struct schedule_instruction * sinst)
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{
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DBG("%i: commit\n", sinst->Instruction->IP);
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DBG("%i: commit score = %d\n", sinst->Instruction->IP, sinst->Score);
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commit_update_reads(s, sinst);
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commit_update_writes(s, sinst);
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if (get_tex_read_count(sinst) > 0) {
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sinst->Instruction->U.P.SemWait = 1;
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notify_sem_wait(s);
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}
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}
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/**
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@ -277,6 +414,7 @@ static void emit_all_tex(struct schedule_state * s, struct rc_instruction * befo
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struct rc_instruction * inst_begin;
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assert(s->ReadyTEX);
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notify_sem_wait(s);
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/* Node marker for R300 */
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inst_begin = rc_insert_new_instruction(s->C, before->Prev);
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@ -308,6 +446,12 @@ static void emit_all_tex(struct schedule_state * s, struct rc_instruction * befo
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while(readytex){
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DBG("%i: commit TEX writes\n", readytex->Instruction->IP);
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commit_update_writes(s, readytex);
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/* Set semaphore bits for last TEX instruction in the block */
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if (!readytex->NextReady) {
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readytex->Instruction->U.I.TexSemAcquire = 1;
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readytex->Instruction->U.I.TexSemWait = 1;
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}
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rc_list_add(&s->PendingTEX, rc_list(&s->C->Pool, readytex));
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readytex = readytex->NextReady;
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}
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}
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@ -491,6 +635,9 @@ static int destructive_merge_instructions(
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rgb->ALUResultCompare = alpha->ALUResultCompare;
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}
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/* Copy SemWait */
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rgb->SemWait |= alpha->SemWait;
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return 1;
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}
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@ -824,14 +971,14 @@ static void pair_instructions(struct schedule_state * s)
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&& convert_rgb_to_alpha(s, rgb_ptr)) {
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struct schedule_instruction * pair_ptr;
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remove_inst_from_list(&s->ReadyRGB, rgb_ptr);
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add_inst_to_list_score(&s->ReadyAlpha, rgb_ptr);
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for (pair_ptr = s->ReadyRGB; pair_ptr;
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pair_ptr = pair_ptr->NextReady) {
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if (pair_ptr == rgb_ptr) {
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continue;
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}
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if (merge_instructions(&pair_ptr->Instruction->U.P,
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&rgb_ptr->Instruction->U.P)) {
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remove_inst_from_list(&s->ReadyRGB, rgb_ptr);
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remove_inst_from_list(&s->ReadyAlpha, rgb_ptr);
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remove_inst_from_list(&s->ReadyRGB, pair_ptr);
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pair_ptr->PairedInst = rgb_ptr;
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@ -849,6 +996,68 @@ static void pair_instructions(struct schedule_state * s)
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}
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}
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static void update_max_score(
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struct schedule_state * s,
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struct schedule_instruction ** list,
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int * max_score,
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struct schedule_instruction ** max_inst_out,
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struct schedule_instruction *** list_out)
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{
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struct schedule_instruction * list_ptr;
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for (list_ptr = *list; list_ptr; list_ptr = list_ptr->NextReady) {
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int score;
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s->CalcScore(list_ptr);
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score = list_ptr->Score;
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if (!*max_inst_out || score > *max_score) {
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*max_score = score;
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*max_inst_out = list_ptr;
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*list_out = list;
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}
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}
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}
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static void emit_instruction(
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struct schedule_state * s,
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struct rc_instruction * before)
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{
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int max_score = -1;
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struct schedule_instruction * max_inst = NULL;
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struct schedule_instruction ** max_list = NULL;
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unsigned tex_count = 0;
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struct schedule_instruction * tex_ptr;
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pair_instructions(s);
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#if VERBOSE
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fprintf(stderr, "Full:\n");
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print_list(s->ReadyFullALU);
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fprintf(stderr, "RGB:\n");
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print_list(s->ReadyRGB);
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fprintf(stderr, "Alpha:\n");
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print_list(s->ReadyAlpha);
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fprintf(stderr, "TEX:\n");
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print_list(s->ReadyTEX);
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#endif
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for (tex_ptr = s->ReadyTEX; tex_ptr; tex_ptr = tex_ptr->NextReady) {
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tex_count++;
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}
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update_max_score(s, &s->ReadyFullALU, &max_score, &max_inst, &max_list);
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update_max_score(s, &s->ReadyRGB, &max_score, &max_inst, &max_list);
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update_max_score(s, &s->ReadyAlpha, &max_score, &max_inst, &max_list);
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if (tex_count >= s->max_tex_group || max_score == -1
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|| (s->TEXCount > 0 && tex_count == s->TEXCount)) {
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emit_all_tex(s, before);
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} else {
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remove_inst_from_list(max_list, max_inst);
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rc_insert_instruction(before->Prev, max_inst->Instruction);
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commit_alu_instruction(s, max_inst);
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presub_nop(before->Prev);
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}
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}
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/**
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* Find a good ALU instruction or pair of ALU instruction and emit it.
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@ -860,6 +1069,7 @@ static void pair_instructions(struct schedule_state * s)
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static void emit_one_alu(struct schedule_state *s, struct rc_instruction * before)
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{
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struct schedule_instruction * sinst;
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int rgb_score = -1, alpha_score = -1;
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/* Try to merge RGB and Alpha instructions together. */
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pair_instructions(s);
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@ -871,6 +1081,12 @@ static void emit_one_alu(struct schedule_state *s, struct rc_instruction * befor
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commit_alu_instruction(s, sinst);
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} else {
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if (s->ReadyRGB) {
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rgb_score = s->ReadyRGB->Score;
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}
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if (s->ReadyAlpha) {
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alpha_score = s->ReadyAlpha->Score;
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}
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if (rgb_score > alpha_score) {
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sinst = s->ReadyRGB;
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s->ReadyRGB = s->ReadyRGB->NextReady;
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} else if (s->ReadyAlpha) {
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@ -924,6 +1140,12 @@ static void scan_read(void * data, struct rc_instruction * inst,
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/* Only update the current instruction's dependencies if the
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* register it reads from has been written to in this block. */
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if ((*v)->Writer) {
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if ((*v)->Writer->Instruction->Type ==
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RC_INSTRUCTION_NORMAL) {
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s->Current->TexReadCount++;
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rc_list_add(&((*v)->Writer->TexReaders),
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rc_list(&s->C->Pool, s->Current));
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}
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s->Current->NumDependencies++;
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}
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}
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@ -977,22 +1199,33 @@ static void is_rgb_to_alpha_possible_normal(
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}
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static void schedule_block(struct r300_fragment_program_compiler * c,
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static void schedule_block(struct schedule_state * s,
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struct rc_instruction * begin, struct rc_instruction * end)
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{
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struct schedule_state s;
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unsigned int ip;
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memset(&s, 0, sizeof(s));
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s.C = &c->Base;
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/* Scan instructions for data dependencies */
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ip = 0;
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for(struct rc_instruction * inst = begin; inst != end; inst = inst->Next) {
|
||||
s.Current = memory_pool_malloc(&c->Base.Pool, sizeof(*s.Current));
|
||||
memset(s.Current, 0, sizeof(struct schedule_instruction));
|
||||
s->Current = memory_pool_malloc(&s->C->Pool, sizeof(*s->Current));
|
||||
memset(s->Current, 0, sizeof(struct schedule_instruction));
|
||||
|
||||
s.Current->Instruction = inst;
|
||||
if (inst->Type == RC_INSTRUCTION_NORMAL) {
|
||||
const struct rc_opcode_info * info =
|
||||
rc_get_opcode_info(inst->U.I.Opcode);
|
||||
if (info->HasTexture) {
|
||||
s->TEXCount++;
|
||||
}
|
||||
}
|
||||
|
||||
/* XXX: This causes SemWait to be set for all instructions in
|
||||
* a block if the previous block contained a TEX instruction.
|
||||
* We can do better here, but it will take a lot of work. */
|
||||
if (s->PrevBlockHasTex) {
|
||||
s->Current->TexReadCount = 1;
|
||||
}
|
||||
|
||||
s->Current->Instruction = inst;
|
||||
inst->IP = ip++;
|
||||
|
||||
DBG("%i: Scanning\n", inst->IP);
|
||||
|
|
@ -1001,17 +1234,18 @@ static void schedule_block(struct r300_fragment_program_compiler * c,
|
|||
* counter-intuitive, to account for the case where an
|
||||
* instruction writes to the same register as it reads
|
||||
* from. */
|
||||
rc_for_all_writes_chan(inst, &scan_write, &s);
|
||||
rc_for_all_reads_chan(inst, &scan_read, &s);
|
||||
rc_for_all_writes_chan(inst, &scan_write, s);
|
||||
rc_for_all_reads_chan(inst, &scan_read, s);
|
||||
|
||||
DBG("%i: Has %i dependencies\n", inst->IP, s.Current->NumDependencies);
|
||||
DBG("%i: Has %i dependencies\n", inst->IP, s->Current->NumDependencies);
|
||||
|
||||
if (!s.Current->NumDependencies)
|
||||
instruction_ready(&s, s.Current);
|
||||
if (!s->Current->NumDependencies) {
|
||||
instruction_ready(s, s->Current);
|
||||
}
|
||||
|
||||
/* Get global readers for possible RGB->Alpha conversion. */
|
||||
s.Current->GlobalReaders.ExitOnAbort = 1;
|
||||
rc_get_readers(s.C, inst, &s.Current->GlobalReaders,
|
||||
s->Current->GlobalReaders.ExitOnAbort = 1;
|
||||
rc_get_readers(s->C, inst, &s->Current->GlobalReaders,
|
||||
is_rgb_to_alpha_possible_normal,
|
||||
is_rgb_to_alpha_possible, NULL);
|
||||
}
|
||||
|
|
@ -1021,13 +1255,17 @@ static void schedule_block(struct r300_fragment_program_compiler * c,
|
|||
end->Prev = begin->Prev;
|
||||
|
||||
/* Schedule instructions back */
|
||||
while(!s.C->Error &&
|
||||
(s.ReadyTEX || s.ReadyRGB || s.ReadyAlpha || s.ReadyFullALU)) {
|
||||
if (s.ReadyTEX)
|
||||
emit_all_tex(&s, end);
|
||||
while(!s->C->Error &&
|
||||
(s->ReadyTEX || s->ReadyRGB || s->ReadyAlpha || s->ReadyFullALU)) {
|
||||
if (s->C->is_r500) {
|
||||
emit_instruction(s, end);
|
||||
} else {
|
||||
if (s->ReadyTEX)
|
||||
emit_all_tex(s, end);
|
||||
|
||||
while(!s.C->Error && (s.ReadyFullALU || s.ReadyRGB || s.ReadyAlpha))
|
||||
emit_one_alu(&s, end);
|
||||
while(!s->C->Error && (s->ReadyFullALU || s->ReadyRGB || s->ReadyAlpha))
|
||||
emit_one_alu(s, end);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1042,13 +1280,14 @@ static int is_controlflow(struct rc_instruction * inst)
|
|||
|
||||
void rc_pair_schedule(struct radeon_compiler *cc, void *user)
|
||||
{
|
||||
struct schedule_state s;
|
||||
|
||||
struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc;
|
||||
struct schedule_state s;
|
||||
struct rc_instruction * inst = c->Base.Program.Instructions.Next;
|
||||
|
||||
memset(&s, 0, sizeof(s));
|
||||
s.C = &c->Base;
|
||||
s.CalcScore = calc_score_readers;
|
||||
s.max_tex_group = debug_get_num_option("RADEON_TEX_GROUP", 8);
|
||||
while(inst != &c->Base.Program.Instructions) {
|
||||
struct rc_instruction * first;
|
||||
|
||||
|
|
@ -1063,6 +1302,11 @@ void rc_pair_schedule(struct radeon_compiler *cc, void *user)
|
|||
inst = inst->Next;
|
||||
|
||||
DBG("Schedule one block\n");
|
||||
schedule_block(c, first, inst);
|
||||
memset(s.Temporary, 0, sizeof(s.Temporary));
|
||||
s.TEXCount = 0;
|
||||
schedule_block(&s, first, inst);
|
||||
if (s.PendingTEX) {
|
||||
s.PrevBlockHasTex = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -109,6 +109,10 @@ struct rc_sub_instruction {
|
|||
/** True if tex instruction should do shadow comparison */
|
||||
unsigned int TexShadow:1;
|
||||
|
||||
/**/
|
||||
unsigned int TexSemWait:1;
|
||||
unsigned int TexSemAcquire:1;
|
||||
|
||||
/**R500 Only. How to swizzle the result of a TEX lookup*/
|
||||
unsigned int TexSwizzle:12;
|
||||
/*@}*/
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ struct rc_pair_instruction {
|
|||
unsigned int WriteALUResult:2;
|
||||
unsigned int ALUResultCompare:3;
|
||||
unsigned int Nop:1;
|
||||
unsigned int SemWait:1;
|
||||
};
|
||||
|
||||
typedef void (*rc_pair_foreach_src_fn)
|
||||
|
|
|
|||
|
|
@ -293,10 +293,12 @@ static void rc_print_normal_instruction(FILE * f, struct rc_instruction * inst,
|
|||
}
|
||||
|
||||
if (opcode->HasTexture) {
|
||||
fprintf(f, ", %s%s[%u]",
|
||||
fprintf(f, ", %s%s[%u]%s%s",
|
||||
textarget_to_string(inst->U.I.TexSrcTarget),
|
||||
inst->U.I.TexShadow ? "SHADOW" : "",
|
||||
inst->U.I.TexSrcUnit);
|
||||
inst->U.I.TexSrcUnit,
|
||||
inst->U.I.TexSemWait ? " SEM_WAIT" : "",
|
||||
inst->U.I.TexSemAcquire ? " SEM_ACQUIRE" : "");
|
||||
}
|
||||
|
||||
fprintf(f, ";");
|
||||
|
|
@ -348,6 +350,9 @@ static void rc_print_pair_instruction(FILE * f, struct rc_instruction * fullinst
|
|||
presubtract_op_to_string(
|
||||
inst->Alpha.Src[RC_PAIR_PRESUB_SRC].Index));
|
||||
}
|
||||
if (inst->SemWait) {
|
||||
fprintf(f, " SEM_WAIT");
|
||||
}
|
||||
fprintf(f, "\n");
|
||||
|
||||
if (inst->RGB.Opcode != RC_OPCODE_NOP) {
|
||||
|
|
|
|||
|
|
@ -3244,7 +3244,8 @@ enum {
|
|||
# define R500_INST_TYPE_OUT (1 << 0)
|
||||
# define R500_INST_TYPE_FC (2 << 0)
|
||||
# define R500_INST_TYPE_TEX (3 << 0)
|
||||
# define R500_INST_TEX_SEM_WAIT (1 << 2)
|
||||
# define R500_INST_TEX_SEM_WAIT_SHIFT 2
|
||||
# define R500_INST_TEX_SEM_WAIT (1 << R500_INST_TEX_SEM_WAIT_SHIFT)
|
||||
# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
|
||||
# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
|
||||
|
|
@ -3426,7 +3427,8 @@ enum {
|
|||
# define R500_TEX_INST_LODBIAS (4 << 22)
|
||||
# define R500_TEX_INST_LOD (5 << 22)
|
||||
# define R500_TEX_INST_DXDY (6 << 22)
|
||||
# define R500_TEX_SEM_ACQUIRE (1 << 25)
|
||||
# define R500_TEX_SEM_ACQUIRE_SHIFT 25
|
||||
# define R500_TEX_SEM_ACQUIRE (1 << R500_TEX_SEM_ACQUIRE_SHIFT)
|
||||
# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
|
||||
# define R500_TEX_UNSCALED (1 << 27)
|
||||
#define R300_US_W_FMT 0x46b4
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue