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etnaviv: stop tracking ZS buffer address information multiple times
Same as with the color buffer addresses, we don't need to track the ZS buffer relocs in different members per GPU generation. Simply emit the part that's relevant for the targeted GPU instance. Again TS depth surface base is always the same address as the first depth pipe address, so we can reuse the reloc. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35406>
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parent
393d594df7
commit
162a1cadd0
3 changed files with 5 additions and 17 deletions
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@ -481,7 +481,7 @@ etna_emit_state(struct etna_context *ctx)
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/*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
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if (screen->info->halti < 0 || screen->info->model == 0x880) {
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/*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
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/*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
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}
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/*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
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@ -566,7 +566,7 @@ etna_emit_state(struct etna_context *ctx)
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/*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[0][0]);
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/*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE);
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/*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE);
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/*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE);
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/*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
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/*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
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/*016BC*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE_EXT, ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT);
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}
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@ -177,7 +177,6 @@ struct compiled_framebuffer_state {
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uint32_t GL_MULTI_SAMPLE_CONFIG;
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uint32_t PE_COLOR_FORMAT;
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uint32_t PE_DEPTH_CONFIG;
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struct etna_reloc PE_DEPTH_ADDR;
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struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
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uint32_t PE_DEPTH_STRIDE;
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uint32_t PE_HDEPTH_CONTROL;
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@ -191,7 +190,6 @@ struct compiled_framebuffer_state {
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uint32_t TS_MEM_CONFIG;
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uint32_t TS_DEPTH_CLEAR_VALUE;
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struct etna_reloc TS_DEPTH_STATUS_BASE;
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struct etna_reloc TS_DEPTH_SURFACE_BASE;
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uint32_t TS_COLOR_CLEAR_VALUE;
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uint32_t TS_COLOR_CLEAR_VALUE_EXT;
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struct etna_reloc TS_COLOR_STATUS_BASE;
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@ -347,14 +347,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
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/* merged with depth_stencil_alpha */
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if (screen->info->halti >= 0 && screen->info->model != 0x880) {
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for (int i = 0; i < screen->specs.pixel_pipes; i++) {
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cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
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cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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} else {
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cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
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cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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for (int i = 0; i < screen->specs.pixel_pipes; i++) {
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cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
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cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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}
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cs->PE_DEPTH_STRIDE = zsbuf->level->stride;
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@ -367,9 +362,6 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
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cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
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cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
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if (zsbuf->level->ts_compress_fmt >= 0) {
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@ -386,10 +378,8 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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} else {
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cs->depth_mrd = 0.0f;
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cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
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cs->PE_DEPTH_ADDR.bo = NULL;
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cs->PE_DEPTH_STRIDE = 0;
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cs->TS_DEPTH_STATUS_BASE.bo = NULL;
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cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
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for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
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cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
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