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gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen

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Reviewed-by: Brian Paul <brianp@vmware.com>
This commit is contained in:
Marek Olšák 2018-09-05 21:30:44 -04:00
parent ce432e259d
commit 15fa2c5e35
2 changed files with 25 additions and 0 deletions
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24
src/gallium/auxiliary/util/u_cpu_detect.c
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@ -367,6 +367,28 @@ check_os_arm_support(void)
} }
#endif /* PIPE_ARCH_ARM */ #endif /* PIPE_ARCH_ARM */
static void
get_cpu_topology(void)
{
uint32_t regs[4];
/* Default. This is correct if L3 is not present or there is only one. */
util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
/* AMD Zen */
if (util_cpu_caps.x86_cpu_type == 0x17) {
/* Query the L3 cache topology information. */
cpuid_count(0x8000001D, 3, regs);
unsigned cache_level = (regs[0] >> 5) & 0x7;
unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
if (cache_level == 3)
util_cpu_caps.cores_per_L3 = cores_per_cache;
}
#endif
}
static void static void
util_cpu_detect_once(void) util_cpu_detect_once(void)
{ {
@ -520,6 +542,8 @@ util_cpu_detect_once(void)
check_os_altivec_support(); check_os_altivec_support();
#endif /* PIPE_ARCH_PPC */ #endif /* PIPE_ARCH_PPC */
get_cpu_topology();
#ifdef DEBUG #ifdef DEBUG
if (debug_get_option_dump_cpu()) { if (debug_get_option_dump_cpu()) {
debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus); debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);

1
src/gallium/auxiliary/util/u_cpu_detect.h
View file

@ -51,6 +51,7 @@ struct util_cpu_caps {
/* Feature flags */ /* Feature flags */
int x86_cpu_type; int x86_cpu_type;
unsigned cacheline; unsigned cacheline;
unsigned cores_per_L3;
unsigned has_intel:1; unsigned has_intel:1;
unsigned has_tsc:1; unsigned has_tsc:1;