From 1585a5cc6d124775ee4e9266c4a26fd8f287e102 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 10 Nov 2023 19:14:34 -0500 Subject: [PATCH] nir,amd: add nir_intrinsic_load_debug_log_desc_amd and its use for shader debugging Acked-by: Alyssa Rosenzweig Part-of: --- src/amd/common/ac_nir.c | 23 ++++++++++++++++++++++ src/amd/common/ac_nir.h | 3 +++ src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ 4 files changed, 30 insertions(+) diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c index f96f72ea339..3c485b0b7e8 100644 --- a/src/amd/common/ac_nir.c +++ b/src/amd/common/ac_nir.c @@ -1259,3 +1259,26 @@ ac_nir_lower_legacy_gs(nir_shader *nir, if (progress) nir_metadata_preserve(impl, nir_metadata_none); } + +/* Shader logging function for printing nir_def values. The driver prints this after + * command submission. + * + * Ring buffer layout: {uint32_t num_dwords; vec4; vec4; vec4; ... } + * - The buffer size must be 2^N * 16 + 4 + * - num_dwords is incremented atomically and the ring wraps around, removing + * the oldest entries. + */ +void +ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4) +{ + nir_def *buf = nir_load_debug_log_desc_amd(b); + nir_def *zero = nir_imm_int(b, 0); + + nir_def *max_index = + nir_iadd_imm(b, nir_ushr_imm(b, nir_iadd_imm(b, nir_channel(b, buf, 2), -4), 4), -1); + nir_def *index = nir_ssbo_atomic(b, 32, buf, zero, nir_imm_int(b, 1), + .atomic_op = nir_atomic_op_iadd); + index = nir_iand(b, index, max_index); + nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, index, 16), 4); + nir_store_buffer_amd(b, uvec4, buf, offset, zero, zero); +} diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index 011fd544ec6..9ca8bbe1270 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -352,6 +352,9 @@ typedef struct { bool ac_nir_lower_tex(nir_shader *nir, const ac_nir_lower_tex_options *options); +void +ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4); + #ifdef __cplusplus } #endif diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index db7e90a27ea..eaa6ffd08ac 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -229,6 +229,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_poly_line_smooth_enabled: case nir_intrinsic_load_rasterization_primitive_amd: case nir_intrinsic_load_global_constant_uniform_block_intel: + case nir_intrinsic_load_debug_log_desc_amd: case nir_intrinsic_cmat_length: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 5bfbcd441c1..5cda3025a28 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1737,6 +1737,9 @@ intrinsic("strict_wqm_coord_amd", src_comp=[0], dest_comp=0, bit_sizes=[32], ind intrinsic("cmat_muladd_amd", src_comp=[16, 16, 0], dest_comp=0, bit_sizes=src2, indices=[SATURATE, CMAT_SIGNED_MASK], flags=[CAN_ELIMINATE]) +# Get the debug log buffer descriptor. +intrinsic("load_debug_log_desc_amd", bit_sizes=[32], dest_comp=4, flags=[CAN_ELIMINATE, CAN_REORDER]) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel