diff --git a/src/gallium/frontends/rusticl/core/memory.rs b/src/gallium/frontends/rusticl/core/memory.rs
index 49acefc2e4e..b0a56832faa 100644
--- a/src/gallium/frontends/rusticl/core/memory.rs
+++ b/src/gallium/frontends/rusticl/core/memory.rs
@@ -1195,7 +1195,7 @@ impl Mem {
         lock: &'a mut MutexGuard<Mappings>,
         rw: RWFlags,
     ) -> CLResult<&'a PipeTransfer> {
-        if let Entry::Vacant(e) = lock.tx.entry(&dev) {
+        if let Entry::Vacant(e) = lock.tx.entry(dev) {
             let (tx, res) = if self.is_buffer() {
                 self.tx_raw_async(dev, rw)?
             } else {