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pvr: drop PVRX macro

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All core-specific selections will take place at runtime.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>
This commit is contained in:
Simon Perretta 2024-10-01 15:32:05 +01:00 • committed by Marge Bot
parent cbc9896264
commit 14d7ade582
31 changed files with 686 additions and 687 deletions
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14
src/imagination/vulkan/pvr_blit.c
View file

@ -66,7 +66,7 @@ pvr_transfer_cmd_alloc(struct pvr_cmd_buffer *cmd_buffer)
/* transfer_cmd->mapping_count is already set to zero. */
transfer_cmd->sources[0].filter = PVR_FILTER_POINT;
transfer_cmd->sources[0].resolve_op = PVR_RESOLVE_BLEND;
transfer_cmd->sources[0].addr_mode = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
transfer_cmd->sources[0].addr_mode = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
transfer_cmd->cmd_buffer = cmd_buffer;
return transfer_cmd;
@ -1654,7 +1654,7 @@ static VkResult pvr_clear_color_attachment_static(
pvr_csb_pack (&texture_program.texture_dma_control[0],
PDSINST_DOUT_FIELDS_DOUTD_SRC1,
doutd_src1) {
doutd_src1.dest = PVRX(PDSINST_DOUTD_DEST_COMMON_STORE);
doutd_src1.dest = ROGUE_PDSINST_DOUTD_DEST_COMMON_STORE;
doutd_src1.bsize = shader_info->const_shared_regs;
}
@ -1702,11 +1702,11 @@ static VkResult pvr_clear_color_attachment_static(
sizeinfo1) {
sizeinfo1.pds_texturestatesize = DIV_ROUND_UP(
clear_attachment_program->texture_program_data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE);
sizeinfo1.pds_tempsize =
DIV_ROUND_UP(clear_attachment_program->texture_program_pds_temps_count,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
}
pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SIZEINFO2],
@ -1714,7 +1714,7 @@ static VkResult pvr_clear_color_attachment_static(
sizeinfo2) {
sizeinfo2.usc_sharedsize =
DIV_ROUND_UP(shader_info->const_shared_regs,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
}
/* Dummy coefficient loading program. */
@ -1737,7 +1737,7 @@ static VkResult pvr_clear_color_attachment_static(
if (template_idx & VK_IMAGE_ASPECT_STENCIL_BIT) {
/* clang-format off */
template.config.ispa.sref = stencil & PVRX(TA_STATE_ISPA_SREF_SIZE_MAX);
template.config.ispa.sref = stencil & ROGUE_TA_STATE_ISPA_SREF_SIZE_MAX;
/* clang-format on */
}
@ -2020,7 +2020,7 @@ static void pvr_clear_attachments(struct pvr_cmd_buffer *cmd_buffer,
/* clang-format off */
template.config.ispa.sref =
attachment->clearValue.depthStencil.stencil &
PVRX(TA_STATE_ISPA_SREF_SIZE_MAX);
ROGUE_TA_STATE_ISPA_SREF_SIZE_MAX;
/* clang-format on */
}

2
src/imagination/vulkan/pvr_border.h
View file

@ -32,7 +32,7 @@
#include "util/bitset.h"
#define PVR_BORDER_COLOR_TABLE_NR_ENTRIES \
(PVRX(TEXSTATE_SAMPLER_BORDERCOLOR_INDEX_MAX_SIZE) + 1)
(ROGUE_TEXSTATE_SAMPLER_BORDERCOLOR_INDEX_MAX_SIZE + 1)
#define PVR_BORDER_COLOR_TABLE_NR_BUILTIN_ENTRIES \
(VK_BORDER_COLOR_INT_OPAQUE_WHITE + 1)

54
src/imagination/vulkan/pvr_clear.c
View file

@ -50,7 +50,7 @@ static void pvr_device_setup_graphics_static_clear_ppp_base(
pvr_csb_pack (&base->ppp_ctrl, TA_STATE_PPP_CTRL, ppp_ctrl) {
ppp_ctrl.pretransform = true;
ppp_ctrl.cullmode = PVRX(TA_CULLMODE_NO_CULLING);
ppp_ctrl.cullmode = ROGUE_TA_CULLMODE_NO_CULLING;
}
/* clang-format off */
@ -89,7 +89,7 @@ static void pvr_device_setup_graphics_static_clear_ppp_templates(
}
#define CS_HEADER(cs) \
(struct PVRX(cs)) \
(struct ROGUE_##cs) \
{ \
pvr_cmd_header(cs) \
}
@ -99,21 +99,21 @@ static void pvr_device_setup_graphics_static_clear_ppp_templates(
template->config.ispctl.bpres = true;
template->config.ispa = CS_HEADER(TA_STATE_ISPA);
template->config.ispa.objtype = PVRX(TA_OBJTYPE_TRIANGLE);
template->config.ispa.passtype = PVRX(TA_PASSTYPE_TRANSLUCENT);
template->config.ispa.objtype = ROGUE_TA_OBJTYPE_TRIANGLE;
template->config.ispa.passtype = ROGUE_TA_PASSTYPE_TRANSLUCENT;
template->config.ispa.dwritedisable = !has_depth;
template->config.ispa.dcmpmode = (i == 0) ? PVRX(TA_CMPMODE_NEVER)
: PVRX(TA_CMPMODE_ALWAYS);
template->config.ispa.dcmpmode = (i == 0) ? ROGUE_TA_CMPMODE_NEVER
: ROGUE_TA_CMPMODE_ALWAYS;
template->config.ispa.sref =
has_stencil ? PVRX(TA_STATE_ISPA_SREF_SIZE_MAX) : 0;
has_stencil ? ROGUE_TA_STATE_ISPA_SREF_SIZE_MAX : 0;
pvr_csb_pack (&template->ispb, TA_STATE_ISPB, ispb) {
ispb.scmpmode = PVRX(TA_CMPMODE_ALWAYS);
ispb.sop1 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop2 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.scmpmode = ROGUE_TA_CMPMODE_ALWAYS;
ispb.sop1 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop2 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop3 = has_stencil ? PVRX(TA_ISPB_STENCILOP_REPLACE)
: PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop3 = has_stencil ? ROGUE_TA_ISPB_STENCILOP_REPLACE
: ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.swmask = has_stencil ? 0xFF : 0;
}
@ -121,13 +121,13 @@ static void pvr_device_setup_graphics_static_clear_ppp_templates(
template->config.pds_state = NULL;
template->config.region_clip0 = CS_HEADER(TA_REGION_CLIP0);
template->config.region_clip0.mode = PVRX(TA_REGION_CLIP_MODE_OUTSIDE);
template->config.region_clip0.mode = ROGUE_TA_REGION_CLIP_MODE_OUTSIDE;
template->config.region_clip0.left = 0;
template->config.region_clip0.right = PVRX(TA_REGION_CLIP_MAX);
template->config.region_clip0.right = ROGUE_TA_REGION_CLIP_MAX;
template->config.region_clip1 = CS_HEADER(TA_REGION_CLIP1);
template->config.region_clip1.top = 0;
template->config.region_clip1.bottom = PVRX(TA_REGION_CLIP_MAX);
template->config.region_clip1.bottom = ROGUE_TA_REGION_CLIP_MAX;
template->config.output_sel = CS_HEADER(TA_OUTPUT_SEL);
template->config.output_sel.vtxsize = 4;
@ -238,8 +238,8 @@ static VkResult
pvr_device_init_clear_attachment_programs(struct pvr_device *device)
{
const uint32_t pds_prog_alignment =
MAX2(PVRX(TA_STATE_PDS_TEXUNICODEBASE_ADDR_ALIGNMENT),
PVRX(TA_STATE_PDS_SHADERBASE_ADDR_ALIGNMENT));
MAX2(ROGUE_TA_STATE_PDS_TEXUNICODEBASE_ADDR_ALIGNMENT,
ROGUE_TA_STATE_PDS_SHADERBASE_ADDR_ALIGNMENT);
struct pvr_device_static_clear_state *clear_state =
&device->static_clear_state;
const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
@ -342,7 +342,7 @@ pvr_device_init_clear_attachment_programs(struct pvr_device *device)
pvr_pds_setup_doutu(&pixel_shader_pds_program.usc_task_control,
usc_upload_offset + usc_program_offsets[offset_idx],
clear_attachment_collection[i].info->temps_required,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_set_sizes_pixel_shader(&pixel_shader_pds_program);
@ -403,7 +403,7 @@ pvr_device_init_clear_attachment_programs(struct pvr_device *device)
pvr_pds_setup_doutu(&pixel_shader_pds_program.usc_task_control,
usc_upload_offset + usc_program_offsets[offset_idx],
clear_attachment_collection[i].info->temps_required,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_generate_pixel_shader_program(
@ -666,7 +666,7 @@ void pvr_pds_clear_vertex_shader_program_init_base(
pvr_pds_setup_doutu(&program->usc_task_control,
usc_shader_bo->dev_addr.addr,
0,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
}
@ -875,7 +875,7 @@ void pvr_pack_clear_vdm_state(const struct pvr_device_info *const dev_info,
{
const uint32_t vs_output_size =
DIV_ROUND_UP(vs_output_size_in_bytes,
PVRX(VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE);
const bool needs_instance_count =
!PVR_HAS_FEATURE(dev_info, gs_rta_support) && layer_count > 1;
uint32_t *stream = state_buffer;
@ -898,8 +898,8 @@ void pvr_pack_clear_vdm_state(const struct pvr_device_info *const dev_info,
state0.vs_other_present = true;
state0.cam_size = cam_size;
state0.uvs_scratch_size_select =
PVRX(VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE);
state0.flatshade_control = PVRX(VDMCTRL_FLATSHADE_CONTROL_VERTEX_0);
ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE;
state0.flatshade_control = ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_0;
}
stream += pvr_cmd_length(VDMCTRL_VDM_STATE0);
@ -925,13 +925,13 @@ void pvr_pack_clear_vdm_state(const struct pvr_device_info *const dev_info,
*/
state5.vs_usc_unified_size =
DIV_ROUND_UP(PVR_CLEAR_VERTEX_COORDINATES * sizeof(uint32_t),
PVRX(VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE);
state5.vs_pds_temp_size =
DIV_ROUND_UP(temps,
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE);
state5.vs_pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE);
}
stream += pvr_cmd_length(VDMCTRL_VDM_STATE5);
@ -945,7 +945,7 @@ void pvr_pack_clear_vdm_state(const struct pvr_device_info *const dev_info,
index_list0.index_count_present = true;
index_list0.index_instance_count_present = needs_instance_count;
index_list0.primitive_topology =
PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP);
ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP;
}
stream += pvr_cmd_length(VDMCTRL_INDEX_LIST0);

10
src/imagination/vulkan/pvr_clear.h
View file

@ -92,8 +92,8 @@ struct pvr_static_clear_ppp_template {
* These are initialized and can be modified as needed before emitting them.
*/
struct {
struct PVRX(TA_STATE_ISPCTL) ispctl;
struct PVRX(TA_STATE_ISPA) ispa;
struct ROGUE_TA_STATE_ISPCTL ispctl;
struct ROGUE_TA_STATE_ISPA ispa;
/* In case the template requires_pds_state this needs to be a valid
* pointer to a pre-packed PDS state before emitting.
@ -103,10 +103,10 @@ struct pvr_static_clear_ppp_template {
*/
const uint32_t (*pds_state)[PVR_STATIC_CLEAR_PDS_STATE_COUNT];
struct PVRX(TA_REGION_CLIP0) region_clip0;
struct PVRX(TA_REGION_CLIP1) region_clip1;
struct ROGUE_TA_REGION_CLIP0 region_clip0;
struct ROGUE_TA_REGION_CLIP1 region_clip1;
struct PVRX(TA_OUTPUT_SEL) output_sel;
struct ROGUE_TA_OUTPUT_SEL output_sel;
} config;
};

260
src/imagination/vulkan/pvr_cmd_buffer.c
View file

@ -78,11 +78,11 @@ struct pvr_compute_kernel_info {
uint32_t usc_unified_size;
uint32_t pds_temp_size;
uint32_t pds_data_size;
enum PVRX(CDMCTRL_USC_TARGET) usc_target;
enum ROGUE_CDMCTRL_USC_TARGET usc_target;
bool is_fence;
uint32_t pds_data_offset;
uint32_t pds_code_offset;
enum PVRX(CDMCTRL_SD_TYPE) sd_type;
enum ROGUE_CDMCTRL_SD_TYPE sd_type;
bool usc_common_shared;
uint32_t global_size[PVR_WORKGROUP_DIMENSIONS];
uint32_t local_size[PVR_WORKGROUP_DIMENSIONS];
@ -526,7 +526,7 @@ static VkResult pvr_sub_cmd_gfx_per_job_fragment_programs_create_and_upload(
pvr_pds_setup_doutu(&pixel_event_program.task_control,
usc_eot_program->dev_addr.addr,
usc_temp_count,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
/* TODO: We could skip allocating this and generate directly into the device
@ -645,11 +645,11 @@ static VkResult pvr_setup_texture_state_words(
TEXSTATE_SAMPLER,
sampler) {
sampler.non_normalized_coords = true;
sampler.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.minfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.magfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
sampler.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
}
return VK_SUCCESS;
@ -815,7 +815,7 @@ static VkResult pvr_load_op_pds_data_create_and_upload(
pvr_csb_pack (&program.texture_dma_control[0],
PDSINST_DOUT_FIELDS_DOUTD_SRC1,
value) {
value.dest = PVRX(PDSINST_DOUTD_DEST_COMMON_STORE);
value.dest = ROGUE_PDSINST_DOUTD_DEST_COMMON_STORE;
value.a0 = load_op->shareds_dest_offset;
value.bsize = load_op->shareds_count;
}
@ -892,13 +892,13 @@ static void pvr_pds_bgnd_pack_state(
pvr_csb_pack (&pds_reg_values[2], CR_PDS_BGRND3_SIZEINFO, value) {
value.usc_sharedsize =
DIV_ROUND_UP(load_op->const_shareds_count,
PVRX(CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE);
value.pds_texturestatesize = DIV_ROUND_UP(
load_op_program->data_size,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE);
value.pds_tempsize =
DIV_ROUND_UP(load_op->temps_count,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE);
}
}
@ -1581,16 +1581,16 @@ static VkResult pvr_sub_cmd_gfx_job_init(const struct pvr_device_info *dev_info,
switch (ds_iview->vk.format) {
case VK_FORMAT_D16_UNORM:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_16BITINT);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_16BITINT;
break;
case VK_FORMAT_S8_UINT:
case VK_FORMAT_D32_SFLOAT:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_F32Z);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_F32Z;
break;
case VK_FORMAT_D24_UNORM_S8_UINT:
job->ds.zls_format = PVRX(CR_ZLS_FORMAT_TYPE_24BITINT);
job->ds.zls_format = ROGUE_CR_ZLS_FORMAT_TYPE_24BITINT;
break;
default:
@ -1758,7 +1758,7 @@ pvr_sub_cmd_compute_job_init(const struct pvr_physical_device *pdevice,
}
#define PIXEL_ALLOCATION_SIZE_MAX_IN_BLOCKS \
(1024 / PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE))
(1024 / ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)
static uint32_t
pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
@ -1774,7 +1774,7 @@ pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
dev_runtime_info->cdm_max_local_mem_size_regs;
uint32_t localstore_chunks_count =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs_count),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Ensure that we cannot have more workgroups in a slot than the available
* number of coefficients allow us to have.
@ -1808,7 +1808,7 @@ pvr_compute_flat_slot_size(const struct pvr_physical_device *pdevice,
*/
uint32_t max_common_store_blocks =
DIV_ROUND_UP(max_avail_coeff_regs * 4U,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* (coefficient_memory_pool_size) - (7 * pixel_allocation_size_max)
*/
@ -1977,16 +1977,16 @@ pvr_compute_generate_idfwdf(struct pvr_cmd_buffer *cmd_buffer,
.global_offsets_present = false,
.usc_common_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(cmd_buffer->device->idfwdf_state.usc_shareds),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.usc_unified_size = 0U,
.pds_temp_size = 0U,
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.is_fence = false,
.pds_data_offset = program->data_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_USC),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC,
.usc_common_shared = true,
.pds_code_offset = program->code_offset,
.global_size = { 1U, 1U, 1U },
@ -2021,11 +2021,11 @@ void pvr_compute_generate_fence(struct pvr_cmd_buffer *cmd_buffer,
.pds_temp_size = 0U,
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.is_fence = true,
.pds_data_offset = program->data_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_PDS),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_PDS,
.usc_common_shared = deallocate_shareds,
.pds_code_offset = program->code_offset,
.global_size = { 1U, 1U, 1U },
@ -2271,7 +2271,7 @@ void pvr_reset_graphics_dirty_state(struct pvr_cmd_buffer *const cmd_buffer,
* phase.
*/
cmd_buffer->state.emit_header = (struct PVRX(TA_STATE_HEADER)){
cmd_buffer->state.emit_header = (struct ROGUE_TA_STATE_HEADER){
.pres_stream_out_size = true,
.pres_ppp_ctrl = true,
.pres_varying_word2 = true,
@ -2286,7 +2286,7 @@ void pvr_reset_graphics_dirty_state(struct pvr_cmd_buffer *const cmd_buffer,
.pres_ispctl = true,
};
} else {
struct PVRX(TA_STATE_HEADER) *const emit_header =
struct ROGUE_TA_STATE_HEADER *const emit_header =
&cmd_buffer->state.emit_header;
emit_header->pres_ppp_ctrl = true;
@ -3135,11 +3135,11 @@ static VkResult pvr_cs_write_load_op(struct pvr_cmd_buffer *cmd_buffer,
sizeinfo1.pds_texturestatesize = DIV_ROUND_UP(
shareds_update_program.data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE);
sizeinfo1.pds_tempsize =
DIV_ROUND_UP(load_op->temps_count,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
}
pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SIZEINFO2],
@ -3147,7 +3147,7 @@ static VkResult pvr_cs_write_load_op(struct pvr_cmd_buffer *cmd_buffer,
sizeinfo2) {
sizeinfo2.usc_sharedsize =
DIV_ROUND_UP(load_op->const_shareds_count,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
}
/* Dummy coefficient loading program. */
@ -4310,13 +4310,13 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info = (struct pvr_compute_kernel_info){
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.usc_common_shared = true,
.usc_common_size =
DIV_ROUND_UP(const_shared_regs,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.global_size = { 1, 1, 1 },
.local_size = { 1, 1, 1 },
@ -4334,7 +4334,7 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info.pds_data_offset = state->pds_compute_descriptor_data_offset;
info.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_data_size_in_dwords),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE);
/* Check that we have upload the code section. */
assert(pipeline->descriptor_state.pds_code.code_size);
@ -4345,7 +4345,7 @@ static void pvr_compute_update_shared(struct pvr_cmd_buffer *cmd_buffer,
info.pds_data_offset = program->data_offset;
info.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program->data_size),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE);
info.pds_code_offset = program->code_offset;
}
@ -4379,14 +4379,14 @@ void pvr_compute_update_shared_private(
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.usc_common_size =
DIV_ROUND_UP(const_shared_regs,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pipeline->pds_shared_update_data_size_dw),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
.usc_target = PVRX(CDMCTRL_USC_TARGET_ALL),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ALL,
.pds_data_offset = pipeline->pds_shared_update_data_offset,
.pds_code_offset = pipeline->pds_shared_update_code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_common_shared = true,
.global_size = { 1, 1, 1 },
.local_size = { 1, 1, 1 },
@ -4412,7 +4412,7 @@ pvr_compute_flat_pad_workgroup_size(const struct pvr_physical_device *pdevice,
dev_runtime_info->cdm_max_local_mem_size_regs;
uint32_t coeff_regs_count_aligned =
ALIGN_POT(coeff_regs_count,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE) >> 2U);
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE >> 2U);
/* If the work group size is > ROGUE_MAX_INSTANCES_PER_TASK. We now *always*
* pad the work group size to the next multiple of
@ -4445,22 +4445,22 @@ void pvr_compute_update_kernel_private(
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr = PVR_DEV_ADDR_INVALID,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.pds_temp_size =
DIV_ROUND_UP(pipeline->pds_temps_used << 2U,
PVRX(CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pipeline->pds_data_size_dw),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.pds_data_offset = pipeline->pds_data_offset,
.pds_code_offset = pipeline->pds_code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_unified_size =
DIV_ROUND_UP(pipeline->unified_store_regs_count << 2U,
PVRX(CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE),
/* clang-format off */
.global_size = {
@ -4486,7 +4486,7 @@ void pvr_compute_update_kernel_private(
info.usc_common_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Use a whole slot per workgroup. */
work_size = MAX2(work_size, ROGUE_MAX_INSTANCES_PER_TASK);
@ -4494,7 +4494,7 @@ void pvr_compute_update_kernel_private(
coeff_regs += pipeline->const_shared_regs_count;
if (pipeline->const_shared_regs_count > 0)
info.sd_type = PVRX(CDMCTRL_SD_TYPE_USC);
info.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC;
work_size =
pvr_compute_flat_pad_workgroup_size(pdevice, work_size, coeff_regs);
@ -4530,22 +4530,22 @@ static void pvr_compute_update_kernel(
struct pvr_compute_kernel_info info = {
.indirect_buffer_addr = indirect_addr,
.usc_target = PVRX(CDMCTRL_USC_TARGET_ANY),
.usc_target = ROGUE_CDMCTRL_USC_TARGET_ANY,
.pds_temp_size =
DIV_ROUND_UP(program_info->temps_required << 2U,
PVRX(CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE),
.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(program_info->data_size_in_dwords),
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
.pds_data_offset = pipeline->primary_program.data_offset,
.pds_code_offset = pipeline->primary_program.code_offset,
.sd_type = PVRX(CDMCTRL_SD_TYPE_NONE),
.sd_type = ROGUE_CDMCTRL_SD_TYPE_NONE,
.usc_unified_size =
DIV_ROUND_UP(shader_state->input_register_count << 2U,
PVRX(CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE)),
ROGUE_CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE),
/* clang-format off */
.global_size = {
@ -4569,7 +4569,7 @@ static void pvr_compute_update_kernel(
info.usc_common_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(coeff_regs),
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE);
/* Use a whole slot per workgroup. */
work_size = MAX2(work_size, ROGUE_MAX_INSTANCES_PER_TASK);
@ -4577,7 +4577,7 @@ static void pvr_compute_update_kernel(
coeff_regs += shader_state->const_shared_reg_count;
if (shader_state->const_shared_reg_count > 0)
info.sd_type = PVRX(CDMCTRL_SD_TYPE_USC);
info.sd_type = ROGUE_CDMCTRL_SD_TYPE_USC;
work_size =
pvr_compute_flat_pad_workgroup_size(pdevice, work_size, coeff_regs);
@ -4807,20 +4807,20 @@ pvr_emit_dirty_pds_state(const struct pvr_cmd_buffer *const cmd_buffer,
pvr_csb_set_relocation_mark(csb);
pvr_csb_emit (csb, VDMCTRL_PDS_STATE0, state0) {
state0.usc_target = PVRX(VDMCTRL_USC_TARGET_ALL);
state0.usc_target = ROGUE_VDMCTRL_USC_TARGET_ALL;
state0.usc_common_size =
DIV_ROUND_UP(vertex_stage_state->const_shared_reg_count << 2,
PVRX(VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE);
state0.pds_data_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(vertex_descriptor_state->pds_info.data_size_in_dwords),
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
state1.pds_data_addr = PVR_DEV_ADDR(pds_vertex_descriptor_data_offset);
state1.sd_type = PVRX(VDMCTRL_SD_TYPE_NONE);
state1.sd_type = ROGUE_VDMCTRL_SD_TYPE_NONE;
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
@ -4839,7 +4839,7 @@ static void pvr_setup_output_select(struct pvr_cmd_buffer *const cmd_buffer)
&gfx_pipeline->shader_state.vertex;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
uint32_t output_selects;
@ -4870,9 +4870,9 @@ static void pvr_setup_output_select(struct pvr_cmd_buffer *const cmd_buffer)
static void
pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
struct PVRX(TA_STATE_ISPA) *const ispa_out)
struct ROGUE_TA_STATE_ISPA *const ispa_out)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
const struct pvr_fragment_shader_state *const fragment_shader_state =
&cmd_buffer->state.gfx_pipeline->shader_state.fragment;
const struct pvr_render_pass_info *const pass_info =
@ -4890,8 +4890,8 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
? &pass_info->pass->attachments[depth_stencil_attachment_idx]
: NULL;
const enum PVRX(TA_OBJTYPE)
obj_type = pvr_ta_objtype(dynamic_state->ia.primitive_topology);
const enum ROGUE_TA_OBJTYPE obj_type =
pvr_ta_objtype(dynamic_state->ia.primitive_topology);
const VkImageAspectFlags ds_aspects =
(!rasterizer_discard && attachment)
@ -4926,7 +4926,7 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
*/
line_width = (!!line_width) * (line_width - 1);
line_width = MIN2(line_width, PVRX(TA_STATE_ISPA_POINTLINEWIDTH_SIZE_MAX));
line_width = MIN2(line_width, ROGUE_TA_STATE_ISPA_POINTLINEWIDTH_SIZE_MAX);
/* TODO: Part of the logic in this function is duplicated in another part
* of the code. E.g. the dcmpmode, and sop1/2/3. Could we do this earlier?
@ -4953,10 +4953,10 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
* If not, rename the variable.
*/
pvr_csb_pack (&ispb_stencil_off, TA_STATE_ISPB, ispb) {
ispb.sop3 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop2 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.sop1 = PVRX(TA_ISPB_STENCILOP_KEEP);
ispb.scmpmode = PVRX(TA_CMPMODE_ALWAYS);
ispb.sop3 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop2 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.sop1 = ROGUE_TA_ISPB_STENCILOP_KEEP;
ispb.scmpmode = ROGUE_TA_CMPMODE_ALWAYS;
}
/* FIXME: This logic should be redone and improved. Can we also get rid of
@ -5060,7 +5060,7 @@ pvr_setup_isp_faces_and_control(struct pvr_cmd_buffer *const cmd_buffer,
ispctl.dbenable = !rasterizer_discard &&
dynamic_state->rs.depth_bias.enable &&
obj_type == PVRX(TA_OBJTYPE_TRIANGLE);
obj_type == ROGUE_TA_OBJTYPE_TRIANGLE;
if (!rasterizer_discard && cmd_buffer->state.vis_test_enabled) {
ispctl.vistest = true;
ispctl.visreg = cmd_buffer->state.vis_reg;
@ -5240,11 +5240,11 @@ pvr_get_geom_region_clip_align_size(struct pvr_device_info *const dev_info)
static void
pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
const struct PVRX(TA_STATE_ISPCTL) *const ispctl =
const struct ROGUE_TA_STATE_ISPCTL *const ispctl =
&ppp_state->isp.control_struct;
struct pvr_device_info *const dev_info =
&cmd_buffer->device->pdevice->dev_info;
@ -5344,7 +5344,7 @@ pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
pvr_csb_pack (&ppp_state->region_clipping.word0, TA_REGION_CLIP0, word0) {
word0.right = right;
word0.left = left;
word0.mode = PVRX(TA_REGION_CLIP_MODE_OUTSIDE);
word0.mode = ROGUE_TA_REGION_CLIP_MODE_OUTSIDE;
}
pvr_csb_pack (&ppp_state->region_clipping.word1, TA_REGION_CLIP1, word1) {
@ -5367,9 +5367,9 @@ pvr_setup_isp_depth_bias_scissor_state(struct pvr_cmd_buffer *const cmd_buffer)
static void
pvr_setup_triangle_merging_flag(struct pvr_cmd_buffer *const cmd_buffer,
struct PVRX(TA_STATE_ISPA) * ispa)
struct ROGUE_TA_STATE_ISPA *ispa)
{
struct PVRX(TA_STATE_HEADER) *const header = &cmd_buffer->state.emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &cmd_buffer->state.emit_header;
struct pvr_ppp_state *const ppp_state = &cmd_buffer->state.ppp_state;
uint32_t merge_word;
uint32_t mask;
@ -5378,9 +5378,9 @@ pvr_setup_triangle_merging_flag(struct pvr_cmd_buffer *const cmd_buffer,
/* Disable for lines or punch-through or for DWD and depth compare
* always.
*/
if (ispa->objtype == PVRX(TA_OBJTYPE_LINE) ||
ispa->passtype == PVRX(TA_PASSTYPE_PUNCH_THROUGH) ||
(ispa->dwritedisable && ispa->dcmpmode == PVRX(TA_CMPMODE_ALWAYS))) {
if (ispa->objtype == ROGUE_TA_OBJTYPE_LINE ||
ispa->passtype == ROGUE_TA_PASSTYPE_PUNCH_THROUGH ||
(ispa->dwritedisable && ispa->dcmpmode == ROGUE_TA_CMPMODE_ALWAYS)) {
size_info.pds_tri_merge_disable = true;
}
}
@ -5413,35 +5413,35 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
&fragment->pds_coeff_program;
const struct pvr_physical_device *pdevice = cmd_buffer->device->pdevice;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
const uint32_t pds_uniform_size =
DIV_ROUND_UP(descriptor_shader_state->pds_info.data_size_in_dwords,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE);
const uint32_t pds_varying_state_size =
DIV_ROUND_UP(pds_coeff_program->data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE);
const uint32_t usc_varying_size =
DIV_ROUND_UP(fragment_state->coefficient_size,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE);
const uint32_t pds_temp_size =
DIV_ROUND_UP(fragment_state->pds_temps_count,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
const uint32_t usc_shared_size =
DIV_ROUND_UP(fragment_state->const_shared_reg_count,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
const uint32_t max_tiles_in_flight =
pvr_calc_fscommon_size_and_tiles_in_flight(
&pdevice->dev_info,
&pdevice->dev_runtime_info,
usc_shared_size *
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE,
1);
uint32_t size_info_mask;
uint32_t size_info2;
@ -5514,7 +5514,7 @@ pvr_setup_fragment_state_pointers(struct pvr_cmd_buffer *const cmd_buffer,
static void pvr_setup_viewport(struct pvr_cmd_buffer *const cmd_buffer)
{
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
@ -5567,7 +5567,7 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
&cmd_buffer->vk.dynamic_graphics_state;
const VkPrimitiveTopology topology = dynamic_state->ia.primitive_topology;
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
uint32_t ppp_control;
@ -5576,14 +5576,14 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
control.wclampen = true;
if (topology == VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN)
control.flatshade_vtx = PVRX(TA_FLATSHADE_VTX_VERTEX_1);
control.flatshade_vtx = ROGUE_TA_FLATSHADE_VTX_VERTEX_1;
else
control.flatshade_vtx = PVRX(TA_FLATSHADE_VTX_VERTEX_0);
control.flatshade_vtx = ROGUE_TA_FLATSHADE_VTX_VERTEX_0;
if (dynamic_state->rs.depth_clamp_enable)
control.clip_mode = PVRX(TA_CLIP_MODE_NO_FRONT_OR_REAR);
control.clip_mode = ROGUE_TA_CLIP_MODE_NO_FRONT_OR_REAR;
else
control.clip_mode = PVRX(TA_CLIP_MODE_FRONT_REAR);
control.clip_mode = ROGUE_TA_CLIP_MODE_FRONT_REAR;
/* +--- FrontIsCCW?
* | +--- Cull Front?
@ -5598,16 +5598,16 @@ static void pvr_setup_ppp_control(struct pvr_cmd_buffer *const cmd_buffer)
case VK_CULL_MODE_FRONT_BIT:
if ((dynamic_state->rs.front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE) ^
(dynamic_state->rs.cull_mode == VK_CULL_MODE_FRONT_BIT)) {
control.cullmode = PVRX(TA_CULLMODE_CULL_CW);
control.cullmode = ROGUE_TA_CULLMODE_CULL_CW;
} else {
control.cullmode = PVRX(TA_CULLMODE_CULL_CCW);
control.cullmode = ROGUE_TA_CULLMODE_CULL_CCW;
}
break;
case VK_CULL_MODE_FRONT_AND_BACK:
case VK_CULL_MODE_NONE:
control.cullmode = PVRX(TA_CULLMODE_NO_CULLING);
control.cullmode = ROGUE_TA_CULLMODE_NO_CULLING;
break;
default:
@ -5641,7 +5641,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
{
const bool deferred_secondary = pvr_cmd_uses_deferred_cs_cmds(cmd_buffer);
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
struct pvr_csb *const control_stream = &sub_cmd->control_stream;
struct pvr_ppp_state *const ppp_state = &state->ppp_state;
uint32_t ppp_state_words[PVR_MAX_PPP_STATE_DWORDS];
@ -5653,7 +5653,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
VkResult result;
#if !defined(NDEBUG)
struct PVRX(TA_STATE_HEADER) emit_mask = *header;
struct ROGUE_TA_STATE_HEADER emit_mask = *header;
uint32_t packed_emit_mask;
static_assert(pvr_cmd_length(TA_STATE_HEADER) == 1,
@ -5928,7 +5928,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
cmd);
}
state->emit_header = (struct PVRX(TA_STATE_HEADER)){ 0 };
state->emit_header = (struct ROGUE_TA_STATE_HEADER){ 0 };
return VK_SUCCESS;
}
@ -5939,7 +5939,7 @@ pvr_ppp_state_update_required(const struct pvr_cmd_buffer *cmd_buffer)
const BITSET_WORD *const dynamic_dirty =
cmd_buffer->vk.dynamic_graphics_state.dirty;
const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
const struct PVRX(TA_STATE_HEADER) *const header = &state->emit_header;
const struct ROGUE_TA_STATE_HEADER *const header = &state->emit_header;
/* For push constants we only need to worry if they are updated for the
* fragment stage since we're only updating the pds programs used in the
@ -5990,7 +5990,7 @@ pvr_emit_dirty_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
return VK_SUCCESS;
if (state->dirty.gfx_pipeline_binding) {
struct PVRX(TA_STATE_ISPA) ispa;
struct ROGUE_TA_STATE_ISPA ispa;
pvr_setup_output_select(cmd_buffer);
pvr_setup_isp_faces_and_control(cmd_buffer, &ispa);
@ -6122,8 +6122,8 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
&cmd_buffer->device->pdevice->dev_info;
ASSERTED const uint32_t max_user_vertex_output_components =
pvr_get_max_user_vertex_output_components(dev_info);
struct PVRX(VDMCTRL_VDM_STATE0)
header = { pvr_cmd_header(VDMCTRL_VDM_STATE0) };
struct ROGUE_VDMCTRL_VDM_STATE0 header = { pvr_cmd_header(
VDMCTRL_VDM_STATE0) };
struct vk_dynamic_graphics_state *const dynamic_state =
&cmd_buffer->vk.dynamic_graphics_state;
const struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
@ -6137,7 +6137,7 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
/* CAM Calculations and HW state take vertex size aligned to DWORDS. */
vs_output_size =
DIV_ROUND_UP(vertex_shader_state->vertex_output_size,
PVRX(VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE);
assert(vs_output_size <= max_user_vertex_output_components);
@ -6159,11 +6159,11 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
switch (dynamic_state->ia.primitive_topology) {
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
state0.flatshade_control = PVRX(VDMCTRL_FLATSHADE_CONTROL_VERTEX_1);
state0.flatshade_control = ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_1;
break;
default:
state0.flatshade_control = PVRX(VDMCTRL_FLATSHADE_CONTROL_VERTEX_0);
state0.flatshade_control = ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_0;
break;
}
@ -6190,7 +6190,7 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
* always emitted to the UVB.
*/
state0.uvs_scratch_size_select =
PVRX(VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE);
ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE;
header = state0;
}
@ -6227,13 +6227,13 @@ static void pvr_emit_dirty_vdm_state(struct pvr_cmd_buffer *const cmd_buffer,
state5.vs_usc_common_size = 0U;
state5.vs_usc_unified_size = DIV_ROUND_UP(
usc_unified_store_size_in_bytes,
PVRX(VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE);
state5.vs_pds_temp_size =
DIV_ROUND_UP(state->pds_shader.info->temps_required << 2,
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE);
state5.vs_pds_data_size = DIV_ROUND_UP(
PVR_DW_TO_BYTES(state->pds_shader.info->data_size_in_dwords),
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE);
}
}
@ -6283,10 +6283,10 @@ static VkResult pvr_validate_draw_state(struct pvr_cmd_buffer *cmd_buffer)
compute_overlap)) {
uint32_t coefficient_size =
DIV_ROUND_UP(fragment_state->coefficient_size,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE);
if (coefficient_size >
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_MAX_SIZE))
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_MAX_SIZE)
sub_cmd->disable_compute_overlap = true;
}
@ -6426,27 +6426,27 @@ static uint32_t pvr_get_hw_primitive_topology(VkPrimitiveTopology topology)
{
switch (topology) {
case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_POINT_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_POINT_LIST;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST;
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_FAN);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_FAN;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ;
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST_ADJ;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP_ADJ);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_STRIP_ADJ;
case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
return PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_PATCH_LIST);
return ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_PATCH_LIST;
default:
unreachable("Undefined primitive topology");
}
@ -6461,7 +6461,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_csb *const csb,
pvr_dev_addr_t idx_buffer_addr,
uint32_t idx_stride,
struct PVRX(VDMCTRL_INDEX_LIST0) * list_hdr,
struct ROGUE_VDMCTRL_INDEX_LIST0 *list_hdr,
struct pvr_buffer *buffer,
VkDeviceSize offset,
uint32_t count,
@ -6553,15 +6553,15 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
pvr_csb_set_relocation_mark(csb);
pvr_csb_emit (csb, VDMCTRL_PDS_STATE0, state0) {
state0.usc_target = PVRX(VDMCTRL_USC_TARGET_ANY);
state0.usc_target = ROGUE_VDMCTRL_USC_TARGET_ANY;
state0.pds_temp_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_prog.program.temp_size_aligned),
PVRX(VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE);
state0.pds_data_size =
DIV_ROUND_UP(PVR_DW_TO_BYTES(pds_prog.program.data_size_aligned),
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
@ -6571,8 +6571,8 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
state1.pds_data_addr = PVR_DEV_ADDR(data_offset);
state1.sd_type = PVRX(VDMCTRL_SD_TYPE_PDS);
state1.sd_next_type = PVRX(VDMCTRL_SD_TYPE_NONE);
state1.sd_type = ROGUE_VDMCTRL_SD_TYPE_PDS;
state1.sd_next_type = ROGUE_VDMCTRL_SD_TYPE_NONE;
}
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
@ -6594,7 +6594,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
* before they are ready.
*/
pvr_csb_emit (csb, VDMCTRL_INDEX_LIST0, list0) {
list0.primitive_topology = PVRX(VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST);
list0.primitive_topology = ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY_TRI_LIST;
}
pvr_csb_clear_relocation_mark(csb);
@ -6658,8 +6658,8 @@ static void pvr_emit_vdm_index_list(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
const bool vertex_shader_has_side_effects =
state->gfx_pipeline->shader_state.vertex.stage_state.has_side_effects;
struct PVRX(VDMCTRL_INDEX_LIST0)
list_hdr = { pvr_cmd_header(VDMCTRL_INDEX_LIST0) };
struct ROGUE_VDMCTRL_INDEX_LIST0 list_hdr = { pvr_cmd_header(
VDMCTRL_INDEX_LIST0) };
pvr_dev_addr_t index_buffer_addr = PVR_DEV_ADDR_INVALID;
struct pvr_csb *const csb = &sub_cmd->control_stream;
unsigned int index_stride = 0;
@ -7518,7 +7518,7 @@ void pvr_CmdNextSubpass2(VkCommandBuffer commandBuffer,
/* If hw_subpass_load_op is valid then pvr_write_load_op_control_stream
* has already done a full-screen transparent object.
*/
if (rp_info->isp_userpass == PVRX(CR_ISP_CTL_UPASS_START_SIZE_MAX) &&
if (rp_info->isp_userpass == ROGUE_CR_ISP_CTL_UPASS_START_SIZE_MAX &&
!hw_subpass_load_op) {
pvr_insert_transparent_obj(cmd_buffer, &state->current_sub_cmd->gfx);
}

2
src/imagination/vulkan/pvr_common.h
View file

@ -192,7 +192,7 @@ union pvr_sampler_descriptor {
uint32_t words[PVR_SAMPLER_DESCRIPTOR_SIZE];
struct {
/* Packed PVRX(TEXSTATE_SAMPLER). */
/* Packed ROGUE_TEXSTATE_SAMPLER. */
uint64_t sampler_word;
uint32_t compare_op;
/* TODO: Figure out what this word is for and rename.

8
src/imagination/vulkan/pvr_csb.c
View file

@ -229,7 +229,7 @@ static bool pvr_csb_buffer_extend(struct pvr_csb *csb)
PVR_DW_TO_BYTES(pvr_cmd_length(VDMCTRL_STREAM_LINK0) +
pvr_cmd_length(VDMCTRL_STREAM_LINK1));
const uint8_t stream_reserved_space =
stream_link_space + PVRX(VDMCTRL_GUARD_SIZE_DEFAULT);
stream_link_space + ROGUE_VDMCTRL_GUARD_SIZE_DEFAULT;
const uint32_t cache_line_size =
rogue_get_slc_cache_line_size(&csb->device->pdevice->dev_info);
size_t current_state_update_size = 0;
@ -244,8 +244,8 @@ static bool pvr_csb_buffer_extend(struct pvr_csb *csb)
(pvr_cmd_length(CDMCTRL_STREAM_LINK0) +
pvr_cmd_length(CDMCTRL_STREAM_LINK1)));
STATIC_ASSERT(PVRX(VDMCTRL_GUARD_SIZE_DEFAULT) ==
PVRX(CDMCTRL_GUARD_SIZE_DEFAULT));
STATIC_ASSERT(ROGUE_VDMCTRL_GUARD_SIZE_DEFAULT ==
ROGUE_CDMCTRL_GUARD_SIZE_DEFAULT);
result = pvr_bo_alloc(csb->device,
csb->device->heaps.general_heap,
@ -372,7 +372,7 @@ VkResult pvr_csb_copy(struct pvr_csb *csb_dst, struct pvr_csb *csb_src)
const uint8_t stream_reserved_space =
PVR_DW_TO_BYTES(pvr_cmd_length(VDMCTRL_STREAM_LINK0) +
pvr_cmd_length(VDMCTRL_STREAM_LINK1)) +
PVRX(VDMCTRL_GUARD_SIZE_DEFAULT);
ROGUE_VDMCTRL_GUARD_SIZE_DEFAULT;
const uint32_t size =
util_dynarray_num_elements(&csb_src->deferred_cs_mem, char);
const uint8_t *start = util_dynarray_begin(&csb_src->deferred_cs_mem);

19
src/imagination/vulkan/pvr_csb.h
View file

@ -247,12 +247,11 @@ void pvr_csb_dump(const struct pvr_csb *csb,
uint32_t frame_num,
uint32_t job_num);
#define PVRX(x) ROGUE_##x
#define pvr_cmd_length(x) PVRX(x##_length)
#define pvr_cmd_header(x) PVRX(x##_header)
#define pvr_cmd_pack(x) PVRX(x##_pack)
#define pvr_cmd_unpack(x) PVRX(x##_unpack)
#define pvr_cmd_enum_to_str(x) PVRX(x##_to_str)
#define pvr_cmd_length(x) ROGUE_##x##_length
#define pvr_cmd_header(x) ROGUE_##x##_header
#define pvr_cmd_pack(x) ROGUE_##x##_pack
#define pvr_cmd_unpack(x) ROGUE_##x##_unpack
#define pvr_cmd_enum_to_str(x) ROGUE_##x##_to_str
/**
* \brief Merges dwords0 and dwords1 arrays and stores the result into the
@ -285,7 +284,7 @@ void pvr_csb_dump(const struct pvr_csb *csb,
* information before it's packed.
*/
#define pvr_csb_emit(csb, cmd, name) \
for (struct PVRX(cmd) \
for (struct ROGUE_##cmd \
name = { pvr_cmd_header(cmd) }, \
*_dst = pvr_csb_alloc_dwords(csb, pvr_cmd_length(cmd)); \
__builtin_expect(_dst != NULL, 1); \
@ -332,8 +331,8 @@ void pvr_csb_dump(const struct pvr_csb *csb,
* state information before it's packed.
*/
#define pvr_csb_pack(_dst, cmd, name) \
for (struct PVRX(cmd) name = { pvr_cmd_header(cmd) }, \
*_loop_terminate = &name; \
for (struct ROGUE_##cmd name = { pvr_cmd_header(cmd) }, \
*_loop_terminate = &name; \
__builtin_expect(_loop_terminate != NULL, 1); \
({ \
STATIC_ASSERT(sizeof(*(_dst)) == \
@ -353,7 +352,7 @@ void pvr_csb_dump(const struct pvr_csb *csb,
*/
#define pvr_csb_unpack(_src, cmd) \
({ \
struct PVRX(cmd) _name; \
struct ROGUE_##cmd _name; \
STATIC_ASSERT(sizeof(*(_src)) == PVR_DW_TO_BYTES(pvr_cmd_length(cmd))); \
pvr_cmd_unpack(cmd)((_src), &_name); \
_name; \

76
src/imagination/vulkan/pvr_csb_enum_helpers.h
View file

@ -52,19 +52,19 @@ pvr_cmd_stream_type_to_str(const enum pvr_cmd_stream_type stream_type)
/* TODO: Use VkSampleCountFlagBits as param type? */
/* clang-format off */
static inline enum PVRX(CR_ISP_AA_MODE_TYPE)
static inline enum ROGUE_CR_ISP_AA_MODE_TYPE
pvr_cr_isp_aa_mode_type(uint32_t samples)
/* clang-format on */
{
switch (samples) {
case 1:
return PVRX(CR_ISP_AA_MODE_TYPE_AA_NONE);
return ROGUE_CR_ISP_AA_MODE_TYPE_AA_NONE;
case 2:
return PVRX(CR_ISP_AA_MODE_TYPE_AA_2X);
return ROGUE_CR_ISP_AA_MODE_TYPE_AA_2X;
case 4:
return PVRX(CR_ISP_AA_MODE_TYPE_AA_4X);
return ROGUE_CR_ISP_AA_MODE_TYPE_AA_4X;
case 8:
return PVRX(CR_ISP_AA_MODE_TYPE_AA_8X);
return ROGUE_CR_ISP_AA_MODE_TYPE_AA_8X;
default:
unreachable("Unsupported number of samples");
}
@ -72,16 +72,16 @@ pvr_cr_isp_aa_mode_type(uint32_t samples)
/* clang-format off */
static inline bool
pvr_zls_format_type_is_packed(enum PVRX(CR_ZLS_FORMAT_TYPE) type)
pvr_zls_format_type_is_packed(enum ROGUE_CR_ZLS_FORMAT_TYPE type)
/* clang-format on */
{
switch (type) {
case PVRX(CR_ZLS_FORMAT_TYPE_24BITINT):
case PVRX(CR_ZLS_FORMAT_TYPE_F64Z):
case ROGUE_CR_ZLS_FORMAT_TYPE_24BITINT:
case ROGUE_CR_ZLS_FORMAT_TYPE_F64Z:
return true;
case PVRX(CR_ZLS_FORMAT_TYPE_F32Z):
case PVRX(CR_ZLS_FORMAT_TYPE_16BITINT):
case ROGUE_CR_ZLS_FORMAT_TYPE_F32Z:
case ROGUE_CR_ZLS_FORMAT_TYPE_16BITINT:
return false;
default:
@ -91,16 +91,16 @@ pvr_zls_format_type_is_packed(enum PVRX(CR_ZLS_FORMAT_TYPE) type)
/* clang-format off */
static inline bool
pvr_zls_format_type_is_int(enum PVRX(CR_ZLS_FORMAT_TYPE) type)
pvr_zls_format_type_is_int(enum ROGUE_CR_ZLS_FORMAT_TYPE type)
/* clang-format on */
{
switch (type) {
case PVRX(CR_ZLS_FORMAT_TYPE_24BITINT):
case PVRX(CR_ZLS_FORMAT_TYPE_16BITINT):
case ROGUE_CR_ZLS_FORMAT_TYPE_24BITINT:
case ROGUE_CR_ZLS_FORMAT_TYPE_16BITINT:
return true;
case PVRX(CR_ZLS_FORMAT_TYPE_F32Z):
case PVRX(CR_ZLS_FORMAT_TYPE_F64Z):
case ROGUE_CR_ZLS_FORMAT_TYPE_F32Z:
case ROGUE_CR_ZLS_FORMAT_TYPE_F64Z:
return false;
default:
@ -113,17 +113,17 @@ pvr_zls_format_type_is_int(enum PVRX(CR_ZLS_FORMAT_TYPE) type)
******************************************************************************/
/* clang-format off */
static inline enum PVRX(PDSINST_DOUTU_SAMPLE_RATE)
static inline enum ROGUE_PDSINST_DOUTU_SAMPLE_RATE
pvr_pdsinst_doutu_sample_rate(enum pvr_msaa_mode msaa_mode)
/* clang-format on */
{
switch (msaa_mode) {
case PVR_MSAA_MODE_PIXEL:
return PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE);
return ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE;
case PVR_MSAA_MODE_SELECTIVE:
return PVRX(PDSINST_DOUTU_SAMPLE_RATE_SELECTIVE);
return ROGUE_PDSINST_DOUTU_SAMPLE_RATE_SELECTIVE;
case PVR_MSAA_MODE_FULL:
return PVRX(PDSINST_DOUTU_SAMPLE_RATE_FULL);
return ROGUE_PDSINST_DOUTU_SAMPLE_RATE_FULL;
default:
unreachable("Undefined MSAA mode.");
}
@ -176,39 +176,39 @@ pvr_pbestate_source_pos(enum pvr_pbe_source_start_pos pos)
TA
******************************************************************************/
static inline enum PVRX(TA_CMPMODE) pvr_ta_cmpmode(VkCompareOp op)
static inline enum ROGUE_TA_CMPMODE pvr_ta_cmpmode(VkCompareOp op)
{
/* enum values are identical, so we can just cast the input directly. */
return (enum PVRX(TA_CMPMODE))op;
return (enum ROGUE_TA_CMPMODE)op;
}
static inline enum PVRX(TA_ISPB_STENCILOP) pvr_ta_stencilop(VkStencilOp op)
static inline enum ROGUE_TA_ISPB_STENCILOP pvr_ta_stencilop(VkStencilOp op)
{
/* enum values are identical, so we can just cast the input directly. */
return (enum PVRX(TA_ISPB_STENCILOP))op;
return (enum ROGUE_TA_ISPB_STENCILOP)op;
}
/* clang-format off */
static inline enum PVRX(TA_OBJTYPE)
static inline enum ROGUE_TA_OBJTYPE
pvr_ta_objtype(VkPrimitiveTopology topology)
/* clang-format on */
{
switch (topology) {
case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
return PVRX(TA_OBJTYPE_SPRITE_01UV);
return ROGUE_TA_OBJTYPE_SPRITE_01UV;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
return PVRX(TA_OBJTYPE_LINE);
return ROGUE_TA_OBJTYPE_LINE;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
return PVRX(TA_OBJTYPE_TRIANGLE);
return ROGUE_TA_OBJTYPE_TRIANGLE;
default:
unreachable("Invalid topology.");
@ -220,10 +220,10 @@ pvr_ta_objtype(VkPrimitiveTopology topology)
TEXSTATE
******************************************************************************/
static inline enum PVRX(TEXSTATE_CMP_MODE) pvr_texstate_cmpmode(VkCompareOp op)
static inline enum ROGUE_TEXSTATE_CMP_MODE pvr_texstate_cmpmode(VkCompareOp op)
{
/* enum values are identical, so we can just cast the input directly. */
return (enum PVRX(TEXSTATE_CMP_MODE))op;
return (enum ROGUE_TEXSTATE_CMP_MODE)op;
}
/******************************************************************************
@ -232,31 +232,31 @@ static inline enum PVRX(TEXSTATE_CMP_MODE) pvr_texstate_cmpmode(VkCompareOp op)
/* clang-format off */
static inline uint32_t
pvr_vdmctrl_index_size_nr_bytes(enum PVRX(VDMCTRL_INDEX_SIZE) index_size)
pvr_vdmctrl_index_size_nr_bytes(enum ROGUE_VDMCTRL_INDEX_SIZE index_size)
/* clang-format on */
{
switch (index_size) {
case PVRX(VDMCTRL_INDEX_SIZE_B8):
case ROGUE_VDMCTRL_INDEX_SIZE_B8:
return 1;
case PVRX(VDMCTRL_INDEX_SIZE_B16):
case ROGUE_VDMCTRL_INDEX_SIZE_B16:
return 2;
case PVRX(VDMCTRL_INDEX_SIZE_B32):
case ROGUE_VDMCTRL_INDEX_SIZE_B32:
return 4;
default:
return 0;
}
}
static enum PVRX(VDMCTRL_INDEX_SIZE)
pvr_vdmctrl_index_size_from_type(VkIndexType type)
static enum ROGUE_VDMCTRL_INDEX_SIZE
pvr_vdmctrl_index_size_from_type(VkIndexType type)
{
switch (type) {
case VK_INDEX_TYPE_UINT32:
return PVRX(VDMCTRL_INDEX_SIZE_B32);
return ROGUE_VDMCTRL_INDEX_SIZE_B32;
case VK_INDEX_TYPE_UINT16:
return PVRX(VDMCTRL_INDEX_SIZE_B16);
return ROGUE_VDMCTRL_INDEX_SIZE_B16;
case VK_INDEX_TYPE_UINT8_KHR:
return PVRX(VDMCTRL_INDEX_SIZE_B8);
return ROGUE_VDMCTRL_INDEX_SIZE_B8;
default:
unreachable("Invalid index type");
}

80
src/imagination/vulkan/pvr_device.c
View file

@ -1178,7 +1178,7 @@ uint32_t pvr_calc_fscommon_size_and_tiles_in_flight(
max_common_size = MIN2(max_common_size, ROGUE_MAX_PIXEL_SHARED_REGISTERS);
max_common_size =
ROUND_DOWN_TO(max_common_size,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
return max_common_size;
}
@ -1351,10 +1351,10 @@ VkResult pvr_pds_compute_shader_create_and_upload(
result = pvr_gpu_upload_pds(device,
data_buffer,
program->data_size,
PVRX(CDMCTRL_KERNEL1_DATA_ADDR_ALIGNMENT),
ROGUE_CDMCTRL_KERNEL1_DATA_ADDR_ALIGNMENT,
code_buffer,
program->code_size / sizeof(uint32_t),
PVRX(CDMCTRL_KERNEL2_CODE_ADDR_ALIGNMENT),
ROGUE_CDMCTRL_KERNEL2_CODE_ADDR_ALIGNMENT,
cache_line_size,
pds_upload_out);
@ -1422,7 +1422,7 @@ static VkResult pvr_pds_idfwdf_programs_create_and_upload(
pvr_pds_setup_doutu(&program.usc_task_control,
usc_addr.addr,
temps,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_vertex_shader_sa(&program, NULL, PDS_GENERATE_SIZES, dev_info);
@ -1574,10 +1574,10 @@ static VkResult pvr_device_init_compute_idfwdf_state(struct pvr_device *device)
/* Pack state words. */
pvr_csb_pack (&sampler_state[0], TEXSTATE_SAMPLER, sampler) {
sampler.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
sampler.magfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
sampler.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
}
/* clang-format off */
@ -1718,7 +1718,7 @@ static VkResult pvr_device_init_nop_program(struct pvr_device *device)
pvr_pds_setup_doutu(&program.usc_task_control,
device->nop_program.usc->dev_addr.addr,
0U,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_set_sizes_pixel_shader(&program);
@ -1842,13 +1842,13 @@ err_release_lock:
static void pvr_device_init_default_sampler_state(struct pvr_device *device)
{
pvr_csb_pack (&device->input_attachment_sampler, TEXSTATE_SAMPLER, sampler) {
sampler.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_w = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
sampler.magfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.minfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.anisoctl = PVRX(TEXSTATE_ANISOCTL_DISABLED);
sampler.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_w = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
sampler.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.anisoctl = ROGUE_TEXSTATE_ANISOCTL_DISABLED;
sampler.non_normalized_coords = true;
}
}
@ -2830,12 +2830,12 @@ pvr_framebuffer_create_ppp_state(struct pvr_device *device,
term0.clip_right =
DIV_ROUND_UP(
framebuffer->width,
PVRX(TA_STATE_TERMINATE0_CLIP_RIGHT_BLOCK_SIZE_IN_PIXELS)) -
ROGUE_TA_STATE_TERMINATE0_CLIP_RIGHT_BLOCK_SIZE_IN_PIXELS) -
1;
term0.clip_bottom =
DIV_ROUND_UP(
framebuffer->height,
PVRX(TA_STATE_TERMINATE0_CLIP_BOTTOM_BLOCK_SIZE_IN_PIXELS)) -
ROGUE_TA_STATE_TERMINATE0_CLIP_BOTTOM_BLOCK_SIZE_IN_PIXELS) -
1;
}
@ -3062,9 +3062,9 @@ pvr_sampler_get_hw_filter_from_vk(const struct pvr_device_info *dev_info,
{
switch (filter) {
case VK_FILTER_NEAREST:
return PVRX(TEXSTATE_FILTER_POINT);
return ROGUE_TEXSTATE_FILTER_POINT;
case VK_FILTER_LINEAR:
return PVRX(TEXSTATE_FILTER_LINEAR);
return ROGUE_TEXSTATE_FILTER_LINEAR;
default:
unreachable("Unknown filter type.");
}
@ -3075,15 +3075,15 @@ pvr_sampler_get_hw_addr_mode_from_vk(VkSamplerAddressMode addr_mode)
{
switch (addr_mode) {
case VK_SAMPLER_ADDRESS_MODE_REPEAT:
return PVRX(TEXSTATE_ADDRMODE_REPEAT);
return ROGUE_TEXSTATE_ADDRMODE_REPEAT;
case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
return PVRX(TEXSTATE_ADDRMODE_FLIP);
return ROGUE_TEXSTATE_ADDRMODE_FLIP;
case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
return PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
return ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
return PVRX(TEXSTATE_ADDRMODE_FLIP_ONCE_THEN_CLAMP);
return ROGUE_TEXSTATE_ADDRMODE_FLIP_ONCE_THEN_CLAMP;
case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
return PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_BORDER);
return ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_BORDER;
default:
unreachable("Invalid sampler address mode.");
}
@ -3160,14 +3160,14 @@ VkResult pvr_CreateSampler(VkDevice _device,
TEXSTATE_SAMPLER,
word) {
const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
const float lod_clamp_max = (float)PVRX(TEXSTATE_CLAMP_MAX) /
(1 << PVRX(TEXSTATE_CLAMP_FRACTIONAL_BITS));
const float max_dadjust = ((float)(PVRX(TEXSTATE_DADJUST_MAX_UINT) -
PVRX(TEXSTATE_DADJUST_ZERO_UINT))) /
(1 << PVRX(TEXSTATE_DADJUST_FRACTIONAL_BITS));
const float min_dadjust = ((float)(PVRX(TEXSTATE_DADJUST_MIN_UINT) -
PVRX(TEXSTATE_DADJUST_ZERO_UINT))) /
(1 << PVRX(TEXSTATE_DADJUST_FRACTIONAL_BITS));
const float lod_clamp_max = (float)ROGUE_TEXSTATE_CLAMP_MAX /
(1 << ROGUE_TEXSTATE_CLAMP_FRACTIONAL_BITS);
const float max_dadjust = ((float)(ROGUE_TEXSTATE_DADJUST_MAX_UINT -
ROGUE_TEXSTATE_DADJUST_ZERO_UINT)) /
(1 << ROGUE_TEXSTATE_DADJUST_FRACTIONAL_BITS);
const float min_dadjust = ((float)(ROGUE_TEXSTATE_DADJUST_MIN_UINT -
ROGUE_TEXSTATE_DADJUST_ZERO_UINT)) /
(1 << ROGUE_TEXSTATE_DADJUST_FRACTIONAL_BITS);
word.magfilter = pvr_sampler_get_hw_filter_from_vk(dev_info, mag_filter);
word.minfilter = pvr_sampler_get_hw_filter_from_vk(dev_info, min_filter);
@ -3183,10 +3183,10 @@ VkResult pvr_CreateSampler(VkDevice _device,
pvr_sampler_get_hw_addr_mode_from_vk(pCreateInfo->addressModeW);
/* TODO: Figure out defines for these. */
if (word.addrmode_u == PVRX(TEXSTATE_ADDRMODE_FLIP))
if (word.addrmode_u == ROGUE_TEXSTATE_ADDRMODE_FLIP)
sampler->descriptor.data.word3 |= 0x40000000;
if (word.addrmode_v == PVRX(TEXSTATE_ADDRMODE_FLIP))
if (word.addrmode_v == ROGUE_TEXSTATE_ADDRMODE_FLIP)
sampler->descriptor.data.word3 |= 0x20000000;
/* The Vulkan 1.0.205 spec says:
@ -3195,13 +3195,13 @@ VkResult pvr_CreateSampler(VkDevice _device,
* VkPhysicalDeviceLimits::maxSamplerLodBias.
*/
word.dadjust =
PVRX(TEXSTATE_DADJUST_ZERO_UINT) +
ROGUE_TEXSTATE_DADJUST_ZERO_UINT +
util_signed_fixed(
CLAMP(pCreateInfo->mipLodBias, min_dadjust, max_dadjust),
PVRX(TEXSTATE_DADJUST_FRACTIONAL_BITS));
ROGUE_TEXSTATE_DADJUST_FRACTIONAL_BITS);
/* Anisotropy is not supported for now. */
word.anisoctl = PVRX(TEXSTATE_ANISOCTL_DISABLED);
word.anisoctl = ROGUE_TEXSTATE_ANISOCTL_DISABLED;
if (PVR_HAS_QUIRK(&device->pdevice->dev_info, 51025) &&
pCreateInfo->mipmapMode == VK_SAMPLER_MIPMAP_MODE_NEAREST) {
@ -3219,11 +3219,11 @@ VkResult pvr_CreateSampler(VkDevice _device,
min_lod = pCreateInfo->minLod + lod_rounding_bias;
word.minlod = util_unsigned_fixed(CLAMP(min_lod, 0.0f, lod_clamp_max),
PVRX(TEXSTATE_CLAMP_FRACTIONAL_BITS));
ROGUE_TEXSTATE_CLAMP_FRACTIONAL_BITS);
max_lod = pCreateInfo->maxLod + lod_rounding_bias;
word.maxlod = util_unsigned_fixed(CLAMP(max_lod, 0.0f, lod_clamp_max),
PVRX(TEXSTATE_CLAMP_FRACTIONAL_BITS));
ROGUE_TEXSTATE_CLAMP_FRACTIONAL_BITS);
word.bordercolor_index = border_color_table_index;

218
src/imagination/vulkan/pvr_dump_csb.c
View file

@ -177,7 +177,7 @@ pvr_dump_csb_block_take(struct pvr_dump_csb_block_ctx *const restrict ctx,
#define pvr_dump_csb_block_take_packed(ctx, cmd, dest) \
({ \
struct pvr_dump_csb_block_ctx *const _block_ctx = (ctx); \
struct PVRX(cmd) *const _dest = (dest); \
struct ROGUE_##cmd *const _dest = (dest); \
const void *const _ptr = \
pvr_dump_csb_block_take(_block_ctx, pvr_cmd_length(cmd)); \
if (_ptr) { \
@ -239,18 +239,18 @@ print_block_cdmctrl_kernel(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(CDMCTRL_KERNEL0) kernel0 = { 0 };
struct PVRX(CDMCTRL_KERNEL1) kernel1 = { 0 };
struct PVRX(CDMCTRL_KERNEL2) kernel2 = { 0 };
struct PVRX(CDMCTRL_KERNEL3) kernel3 = { 0 };
struct PVRX(CDMCTRL_KERNEL4) kernel4 = { 0 };
struct PVRX(CDMCTRL_KERNEL5) kernel5 = { 0 };
struct PVRX(CDMCTRL_KERNEL6) kernel6 = { 0 };
struct PVRX(CDMCTRL_KERNEL7) kernel7 = { 0 };
struct PVRX(CDMCTRL_KERNEL8) kernel8 = { 0 };
struct PVRX(CDMCTRL_KERNEL9) kernel9 = { 0 };
struct PVRX(CDMCTRL_KERNEL10) kernel10 = { 0 };
struct PVRX(CDMCTRL_KERNEL11) kernel11 = { 0 };
struct ROGUE_CDMCTRL_KERNEL0 kernel0 = { 0 };
struct ROGUE_CDMCTRL_KERNEL1 kernel1 = { 0 };
struct ROGUE_CDMCTRL_KERNEL2 kernel2 = { 0 };
struct ROGUE_CDMCTRL_KERNEL3 kernel3 = { 0 };
struct ROGUE_CDMCTRL_KERNEL4 kernel4 = { 0 };
struct ROGUE_CDMCTRL_KERNEL5 kernel5 = { 0 };
struct ROGUE_CDMCTRL_KERNEL6 kernel6 = { 0 };
struct ROGUE_CDMCTRL_KERNEL7 kernel7 = { 0 };
struct ROGUE_CDMCTRL_KERNEL8 kernel8 = { 0 };
struct ROGUE_CDMCTRL_KERNEL9 kernel9 = { 0 };
struct ROGUE_CDMCTRL_KERNEL10 kernel10 = { 0 };
struct ROGUE_CDMCTRL_KERNEL11 kernel11 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "KERNEL"))
goto end_out;
@ -295,25 +295,25 @@ print_block_cdmctrl_kernel(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&kernel0,
usc_common_size,
PVRX(CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE),
ROGUE_CDMCTRL_KERNEL0_USC_COMMON_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&kernel0,
usc_unified_size,
PVRX(CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE),
ROGUE_CDMCTRL_KERNEL0_USC_UNIFIED_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&kernel0,
pds_temp_size,
PVRX(CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE),
ROGUE_CDMCTRL_KERNEL0_PDS_TEMP_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&kernel0,
pds_data_size,
PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_enum(base_ctx,
&kernel0,
@ -330,7 +330,7 @@ print_block_cdmctrl_kernel(struct pvr_dump_csb_ctx *const csb_ctx,
device,
BUFFER_TYPE_NONE,
PVR_DEV_ADDR_OFFSET(pds_heap_base, kernel1.data_addr.addr),
kernel0.pds_data_size * PVRX(CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE),
kernel0.pds_data_size * ROGUE_CDMCTRL_KERNEL0_PDS_DATA_SIZE_UNIT_SIZE,
"pds_data_size");
if (!ret)
goto end_pop_ctx;
@ -409,8 +409,8 @@ print_block_cdmctrl_stream_link(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(CDMCTRL_STREAM_LINK0) link0 = { 0 };
struct PVRX(CDMCTRL_STREAM_LINK1) link1 = { 0 };
struct ROGUE_CDMCTRL_STREAM_LINK0 link0 = { 0 };
struct ROGUE_CDMCTRL_STREAM_LINK1 link1 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STREAM_LINK"))
goto end_out;
@ -443,7 +443,7 @@ print_block_cdmctrl_stream_terminate(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(CDMCTRL_STREAM_TERMINATE) terminate = { 0 };
struct ROGUE_CDMCTRL_STREAM_TERMINATE terminate = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "TERMINATE"))
goto end_out;
@ -475,8 +475,8 @@ print_block_vdmctrl_ppp_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_PPP_STATE0) state0 = { 0 };
struct PVRX(VDMCTRL_PPP_STATE1) state1 = { 0 };
struct ROGUE_VDMCTRL_PPP_STATE0 state0 = { 0 };
struct ROGUE_VDMCTRL_PPP_STATE1 state1 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "PPP_STATE_UPDATE"))
goto end_out;
@ -519,9 +519,9 @@ print_block_vdmctrl_pds_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_PDS_STATE0) state0 = { 0 };
struct PVRX(VDMCTRL_PDS_STATE1) state1 = { 0 };
struct PVRX(VDMCTRL_PDS_STATE2) state2 = { 0 };
struct ROGUE_VDMCTRL_PDS_STATE0 state0 = { 0 };
struct ROGUE_VDMCTRL_PDS_STATE1 state1 = { 0 };
struct ROGUE_VDMCTRL_PDS_STATE2 state2 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "PDS_STATE_UPDATE"))
goto end_out;
@ -545,25 +545,25 @@ print_block_vdmctrl_pds_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&state0,
usc_common_size,
PVRX(VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state0,
usc_unified_size,
PVRX(VDMCTRL_PDS_STATE0_USC_UNIFIED_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_PDS_STATE0_USC_UNIFIED_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state0,
pds_temp_size,
PVRX(VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_PDS_STATE0_PDS_TEMP_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state0,
pds_data_size,
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_addr_offset(base_ctx,
@ -575,7 +575,7 @@ print_block_vdmctrl_pds_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
device,
BUFFER_TYPE_NONE,
PVR_DEV_ADDR_OFFSET(pds_heap_base, state1.pds_data_addr.addr),
state0.pds_data_size * PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE),
state0.pds_data_size * ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE,
"pds_data_size");
if (!ret)
goto end_pop_ctx;
@ -626,12 +626,12 @@ print_block_vdmctrl_vdm_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_VDM_STATE0) state0 = { 0 };
struct PVRX(VDMCTRL_VDM_STATE1) state1 = { 0 };
struct PVRX(VDMCTRL_VDM_STATE2) state2 = { 0 };
struct PVRX(VDMCTRL_VDM_STATE3) state3 = { 0 };
struct PVRX(VDMCTRL_VDM_STATE4) state4 = { 0 };
struct PVRX(VDMCTRL_VDM_STATE5) state5 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE0 state0 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE1 state1 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE2 state2 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE3 state3 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE4 state4 = { 0 };
struct ROGUE_VDMCTRL_VDM_STATE5 state5 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "VDM_STATE_UPDATE"))
goto end_out;
@ -680,7 +680,7 @@ print_block_vdmctrl_vdm_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
PVR_DEV_ADDR_OFFSET(pds_heap_base,
state2.vs_pds_data_base_addr.addr),
state5.vs_pds_data_size *
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE,
"pds_data_size");
} else {
/* FIXME: Determine the exact size of the PDS data section when no
@ -725,7 +725,7 @@ print_block_vdmctrl_vdm_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&state4,
vs_output_size,
PVRX(VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE4_VS_OUTPUT_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_zero(base_ctx, &state5, vs_max_instances, 32);
@ -733,25 +733,25 @@ print_block_vdmctrl_vdm_state_update(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&state5,
vs_usc_common_size,
PVRX(VDMCTRL_VDM_STATE5_VS_USC_COMMON_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE5_VS_USC_COMMON_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state5,
vs_usc_unified_size,
PVRX(VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE5_VS_USC_UNIFIED_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state5,
vs_pds_temp_size,
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_TEMP_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&state5,
vs_pds_data_size,
PVRX(VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_VDMCTRL_VDM_STATE5_VS_PDS_DATA_SIZE_UNIT_SIZE,
"bytes");
} else {
pvr_dump_field_member_not_present(base_ctx,
@ -803,16 +803,16 @@ print_block_vdmctrl_index_list(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_INDEX_LIST0) index_list0 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST1) index_list1 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST2) index_list2 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST3) index_list3 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST4) index_list4 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST5) index_list5 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST6) index_list6 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST7) index_list7 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST8) index_list8 = { 0 };
struct PVRX(VDMCTRL_INDEX_LIST9) index_list9 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST0 index_list0 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST1 index_list1 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST2 index_list2 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST3 index_list3 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST4 index_list4 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST5 index_list5 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST6 index_list6 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST7 index_list7 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST8 index_list8 = { 0 };
struct ROGUE_VDMCTRL_INDEX_LIST9 index_list9 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "INDEX_LIST"))
goto end_out;
@ -1005,8 +1005,8 @@ print_block_vdmctrl_stream_link(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_STREAM_LINK0) link0 = { 0 };
struct PVRX(VDMCTRL_STREAM_LINK1) link1 = { 0 };
struct ROGUE_VDMCTRL_STREAM_LINK0 link0 = { 0 };
struct ROGUE_VDMCTRL_STREAM_LINK1 link1 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STREAM_LINK"))
goto end_out;
@ -1049,7 +1049,7 @@ print_block_vdmctrl_stream_return(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_STREAM_RETURN) return_ = { 0 };
struct ROGUE_VDMCTRL_STREAM_RETURN return_ = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STREAM_RETURN"))
goto end_out;
@ -1077,7 +1077,7 @@ print_block_vdmctrl_stream_terminate(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(VDMCTRL_STREAM_TERMINATE) terminate = { 0 };
struct ROGUE_VDMCTRL_STREAM_TERMINATE terminate = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "TERMINATE"))
goto end_out;
@ -1102,14 +1102,14 @@ end_out:
static uint32_t
print_block_ppp_state_header(struct pvr_dump_csb_ctx *const csb_ctx,
struct PVRX(TA_STATE_HEADER) *const header_out)
struct ROGUE_TA_STATE_HEADER *const header_out)
{
struct pvr_dump_csb_block_ctx ctx;
struct pvr_dump_ctx *const base_ctx = &ctx.base.base;
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_HEADER) header = { 0 };
struct ROGUE_TA_STATE_HEADER header = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_HEADER"))
goto end_out;
@ -1157,8 +1157,8 @@ end_out:
static void print_block_ppp_state_isp_one_side(
struct pvr_dump_csb_block_ctx *const ctx,
const struct PVRX(TA_STATE_ISPA) *const isp_a,
const struct PVRX(TA_STATE_ISPB) *const isp_b,
const struct ROGUE_TA_STATE_ISPA *const isp_a,
const struct ROGUE_TA_STATE_ISPB *const isp_b,
const bool has_b)
{
struct pvr_dump_ctx *const base_ctx = &ctx->base.base;
@ -1229,12 +1229,12 @@ print_block_ppp_state_isp(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_ISPCTL) isp_ctl = { 0 };
struct PVRX(TA_STATE_ISPA) isp_fa = { 0 };
struct PVRX(TA_STATE_ISPB) isp_fb = { 0 };
struct PVRX(TA_STATE_ISPA) isp_ba = { 0 };
struct PVRX(TA_STATE_ISPB) isp_bb = { 0 };
struct PVRX(TA_STATE_ISPDBSC) isp_dbsc = { 0 };
struct ROGUE_TA_STATE_ISPCTL isp_ctl = { 0 };
struct ROGUE_TA_STATE_ISPA isp_fa = { 0 };
struct ROGUE_TA_STATE_ISPB isp_fb = { 0 };
struct ROGUE_TA_STATE_ISPA isp_ba = { 0 };
struct ROGUE_TA_STATE_ISPB isp_bb = { 0 };
struct ROGUE_TA_STATE_ISPDBSC isp_dbsc = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_ISP"))
goto end_out;
@ -1340,13 +1340,13 @@ print_block_ppp_state_pds(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_PDS_SHADERBASE) shader_base = { 0 };
struct PVRX(TA_STATE_PDS_TEXUNICODEBASE) tex_unicode_base = { 0 };
struct PVRX(TA_STATE_PDS_SIZEINFO1) size_info1 = { 0 };
struct PVRX(TA_STATE_PDS_SIZEINFO2) size_info2 = { 0 };
struct PVRX(TA_STATE_PDS_VARYINGBASE) varying_base = { 0 };
struct PVRX(TA_STATE_PDS_TEXTUREDATABASE) texture_data_base = { 0 };
struct PVRX(TA_STATE_PDS_UNIFORMDATABASE) uniform_data_base = { 0 };
struct ROGUE_TA_STATE_PDS_SHADERBASE shader_base = { 0 };
struct ROGUE_TA_STATE_PDS_TEXUNICODEBASE tex_unicode_base = { 0 };
struct ROGUE_TA_STATE_PDS_SIZEINFO1 size_info1 = { 0 };
struct ROGUE_TA_STATE_PDS_SIZEINFO2 size_info2 = { 0 };
struct ROGUE_TA_STATE_PDS_VARYINGBASE varying_base = { 0 };
struct ROGUE_TA_STATE_PDS_TEXTUREDATABASE texture_data_base = { 0 };
struct ROGUE_TA_STATE_PDS_UNIFORMDATABASE uniform_data_base = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_PDS"))
goto end_out;
@ -1410,38 +1410,38 @@ print_block_ppp_state_pds(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&size_info1,
pds_uniformsize,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&size_info1,
pds_texturestatesize,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&size_info1,
pds_varyingsize,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&size_info1,
usc_varyingsize,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&size_info1,
pds_tempsize,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&size_info2,
usc_sharedsize,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE),
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE,
"words");
pvr_dump_field_member_bool(base_ctx, &size_info2, pds_tri_merge_disable);
pvr_dump_field_member_u32(base_ctx, &size_info2, pds_batchnum);
@ -1506,8 +1506,8 @@ print_block_ppp_region_clip(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_REGION_CLIP0) clip0 = { 0 };
struct PVRX(TA_REGION_CLIP1) clip1 = { 0 };
struct ROGUE_TA_REGION_CLIP0 clip0 = { 0 };
struct ROGUE_TA_REGION_CLIP1 clip1 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "REGION_CLIP"))
goto end_out;
@ -1612,7 +1612,7 @@ print_block_ppp_output_sel(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_OUTPUT_SEL) output_sel = { 0 };
struct ROGUE_TA_OUTPUT_SEL output_sel = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "OUTPUT_SEL"))
goto end_out;
@ -1667,9 +1667,9 @@ print_block_ppp_state_varying(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_VARYING0) varying0 = { 0 };
struct PVRX(TA_STATE_VARYING1) varying1 = { 0 };
struct PVRX(TA_STATE_VARYING2) varying2 = { 0 };
struct ROGUE_TA_STATE_VARYING0 varying0 = { 0 };
struct ROGUE_TA_STATE_VARYING1 varying1 = { 0 };
struct ROGUE_TA_STATE_VARYING2 varying2 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_VARYING"))
goto end_out;
@ -1737,7 +1737,7 @@ print_block_ppp_state_ppp_ctrl(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_PPP_CTRL) ppp_ctrl = { 0 };
struct ROGUE_TA_STATE_PPP_CTRL ppp_ctrl = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_PPP_CTRL"))
goto end_out;
@ -1793,9 +1793,9 @@ print_block_ppp_state_stream_out(struct pvr_dump_csb_ctx *const csb_ctx,
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_STREAM_OUT0) stream_out0 = { 0 };
struct PVRX(TA_STATE_STREAM_OUT1) stream_out1 = { 0 };
struct PVRX(TA_STATE_STREAM_OUT2) stream_out2 = { 0 };
struct ROGUE_TA_STATE_STREAM_OUT0 stream_out0 = { 0 };
struct ROGUE_TA_STATE_STREAM_OUT1 stream_out1 = { 0 };
struct ROGUE_TA_STATE_STREAM_OUT2 stream_out2 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_STREAM_OUT"))
goto end_out;
@ -1853,13 +1853,13 @@ print_block_ppp_state_stream_out(struct pvr_dump_csb_ctx *const csb_ctx,
base_ctx,
&stream_out1,
pds_temp_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_TEMP_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_TEMP_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_u32_scaled_units(
base_ctx,
&stream_out1,
pds_data_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE,
"bytes");
pvr_dump_field_member_bool(base_ctx, &stream_out1, sync);
pvr_dump_field_member_addr_offset(base_ctx,
@ -1899,8 +1899,8 @@ print_block_ppp_state_terminate(struct pvr_dump_csb_ctx *const csb_ctx)
uint32_t words_read = 0;
bool ret = false;
struct PVRX(TA_STATE_TERMINATE0) terminate0 = { 0 };
struct PVRX(TA_STATE_TERMINATE1) terminate1 = { 0 };
struct ROGUE_TA_STATE_TERMINATE0 terminate0 = { 0 };
struct ROGUE_TA_STATE_TERMINATE1 terminate1 = { 0 };
if (!pvr_dump_csb_block_ctx_push(&ctx, csb_ctx, "STATE_TERMINATE"))
goto end_out;
@ -1984,7 +1984,7 @@ static bool print_cdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
return false;
do {
enum PVRX(CDMCTRL_BLOCK_TYPE) block_type;
enum ROGUE_CDMCTRL_BLOCK_TYPE block_type;
const uint32_t *next_word;
uint32_t words_read = 0;
@ -1997,15 +1997,15 @@ static bool print_cdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
block_type =
pvr_csb_unpack(next_word, CDMCTRL_STREAM_TERMINATE).block_type;
switch (block_type) {
case PVRX(CDMCTRL_BLOCK_TYPE_COMPUTE_KERNEL):
case ROGUE_CDMCTRL_BLOCK_TYPE_COMPUTE_KERNEL:
words_read = print_block_cdmctrl_kernel(&ctx, device);
break;
case PVRX(CDMCTRL_BLOCK_TYPE_STREAM_LINK):
case ROGUE_CDMCTRL_BLOCK_TYPE_STREAM_LINK:
words_read = print_block_cdmctrl_stream_link(&ctx);
break;
case PVRX(CDMCTRL_BLOCK_TYPE_STREAM_TERMINATE):
case ROGUE_CDMCTRL_BLOCK_TYPE_STREAM_TERMINATE:
words_read = print_block_cdmctrl_stream_terminate(&ctx);
break;
@ -2020,7 +2020,7 @@ static bool print_cdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
if (!print_block_hex(&ctx.base, words_read))
ret = false;
if (block_type == PVRX(CDMCTRL_BLOCK_TYPE_STREAM_TERMINATE))
if (block_type == ROGUE_CDMCTRL_BLOCK_TYPE_STREAM_TERMINATE)
break;
} while (ret);
@ -2046,7 +2046,7 @@ static bool print_vdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
return false;
do {
enum PVRX(VDMCTRL_BLOCK_TYPE) block_type;
enum ROGUE_VDMCTRL_BLOCK_TYPE block_type;
const uint32_t *next_word;
uint32_t words_read = 0;
@ -2058,31 +2058,31 @@ static bool print_vdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
block_type = pvr_csb_unpack(next_word, VDMCTRL_STREAM_RETURN).block_type;
switch (block_type) {
case PVRX(VDMCTRL_BLOCK_TYPE_PPP_STATE_UPDATE):
case ROGUE_VDMCTRL_BLOCK_TYPE_PPP_STATE_UPDATE:
words_read = print_block_vdmctrl_ppp_state_update(&ctx, device);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_PDS_STATE_UPDATE):
case ROGUE_VDMCTRL_BLOCK_TYPE_PDS_STATE_UPDATE:
words_read = print_block_vdmctrl_pds_state_update(&ctx, device);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_VDM_STATE_UPDATE):
case ROGUE_VDMCTRL_BLOCK_TYPE_VDM_STATE_UPDATE:
words_read = print_block_vdmctrl_vdm_state_update(&ctx, device);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_INDEX_LIST):
case ROGUE_VDMCTRL_BLOCK_TYPE_INDEX_LIST:
words_read = print_block_vdmctrl_index_list(&ctx, device);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_STREAM_LINK):
case ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_LINK:
words_read = print_block_vdmctrl_stream_link(&ctx);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_STREAM_RETURN):
case ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_RETURN:
words_read = print_block_vdmctrl_stream_return(&ctx);
break;
case PVRX(VDMCTRL_BLOCK_TYPE_STREAM_TERMINATE):
case ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_TERMINATE:
words_read = print_block_vdmctrl_stream_terminate(&ctx);
break;
@ -2097,7 +2097,7 @@ static bool print_vdmctrl_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
if (!print_block_hex(&ctx.base, words_read))
ret = false;
if (block_type == PVRX(VDMCTRL_BLOCK_TYPE_STREAM_TERMINATE))
if (block_type == ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_TERMINATE)
break;
} while (ret);
@ -2114,7 +2114,7 @@ static bool print_ppp_buffer(struct pvr_dump_buffer_ctx *const parent_ctx,
uint32_t words_read;
bool ret = false;
struct PVRX(TA_STATE_HEADER) header = { 0 };
struct ROGUE_TA_STATE_HEADER header = { 0 };
if (!pvr_dump_csb_ctx_push(&ctx, parent_ctx))
goto end_out;

18
src/imagination/vulkan/pvr_formats.c
View file

@ -232,9 +232,9 @@ static const struct pvr_format pvr_format_table[] = {
#undef FORMAT_COMPRESSED
#define FORMAT(tex_fmt, pipe_fmt_int, pipe_fmt_float) \
[PVRX(TEXSTATE_FORMAT_##tex_fmt)] = { \
[ROGUE_TEXSTATE_FORMAT_##tex_fmt] = { \
.desc = { \
.tex_format = PVRX(TEXSTATE_FORMAT_##tex_fmt), \
.tex_format = ROGUE_TEXSTATE_FORMAT_##tex_fmt, \
.pipe_format_int = PIPE_FORMAT_##pipe_fmt_int, \
.pipe_format_float = PIPE_FORMAT_##pipe_fmt_float, \
}, \
@ -284,11 +284,11 @@ static const struct pvr_tex_format_table_entry {
#undef FORMAT
#define FORMAT(tex_fmt, pipe_fmt, tex_fmt_simple) \
[PVRX(TEXSTATE_FORMAT_COMPRESSED_##tex_fmt)] = { \
[ROGUE_TEXSTATE_FORMAT_COMPRESSED_##tex_fmt] = { \
.desc = { \
.tex_format = PVRX(TEXSTATE_FORMAT_COMPRESSED_##tex_fmt), \
.tex_format = ROGUE_TEXSTATE_FORMAT_COMPRESSED_##tex_fmt, \
.pipe_format = PIPE_FORMAT_##pipe_fmt, \
.tex_format_simple = PVRX(TEXSTATE_FORMAT_##tex_fmt_simple), \
.tex_format_simple = ROGUE_TEXSTATE_FORMAT_##tex_fmt_simple, \
}, \
.present = true, \
}
@ -335,7 +335,7 @@ pvr_get_tex_format_description(const uint32_t tex_format)
return &pvr_tex_format_table[tex_format].desc;
mesa_logd("Tex format %s (%d) not supported\n",
PVRX(TEXSTATE_FORMAT_to_str)(tex_format),
ROGUE_TEXSTATE_FORMAT_to_str(tex_format),
tex_format);
return NULL;
@ -368,7 +368,7 @@ pvr_get_tex_format_compressed_description(uint32_t tex_format)
return &pvr_tex_format_compressed_table[tex_format].desc;
mesa_logd("Compressed tex format %s (%d) not supported\n",
PVRX(TEXSTATE_FORMAT_COMPRESSED_to_str)(tex_format),
ROGUE_TEXSTATE_FORMAT_COMPRESSED_to_str(tex_format),
tex_format);
return NULL;
@ -397,7 +397,7 @@ uint32_t pvr_get_tex_format_aspect(VkFormat vk_format,
return pvr_format->tex_format;
}
return PVRX(TEXSTATE_FORMAT_INVALID);
return ROGUE_TEXSTATE_FORMAT_INVALID;
}
uint32_t pvr_get_pbe_packmode(VkFormat vk_format)
@ -906,7 +906,7 @@ pvr_get_image_format_properties(struct pvr_physical_device *pdevice,
pImageFormatProperties->maxExtent.depth = PVR_MAX_TEXTURE_EXTENT_Z;
} else {
const uint32_t max_texture_extent_xy =
PVRX(TEXSTATE_IMAGE_WORD0_WIDTH_MAX_SIZE) + 1U;
ROGUE_TEXSTATE_IMAGE_WORD0_WIDTH_MAX_SIZE + 1U;
pImageFormatProperties->maxExtent.width = max_texture_extent_xy;
pImageFormatProperties->maxExtent.height = max_texture_extent_xy;

6
src/imagination/vulkan/pvr_formats.h
View file

@ -39,7 +39,7 @@
*/
#define PVR_CLEAR_COLOR_ARRAY_SIZE 4
#define PVR_TEX_FORMAT_COUNT (PVRX(TEXSTATE_IMAGE_WORD0_TEXFORMAT_MAX_SIZE) + 1)
#define PVR_TEX_FORMAT_COUNT (ROGUE_TEXSTATE_IMAGE_WORD0_TEXFORMAT_MAX_SIZE + 1)
enum pvr_pbe_accum_format {
PVR_PBE_ACCUM_FORMAT_INVALID = 0, /* Explicitly treat 0 as invalid. */
@ -212,8 +212,8 @@ enum pvr_transfer_pbe_pixel_src {
PVR_TRANSFER_PBE_PIXEL_SRC_NUM = 54,
};
/* FIXME: Replace all instances of uint32_t with PVRX(TEXSTATE_FORMAT) or
* PVRX(TEXSTATE_FORMAT_COMPRESSED) after the pvr_common cleanup is complete.
/* FIXME: Replace all instances of uint32_t with ROGUE_TEXSTATE_FORMAT or
* ROGUE_TEXSTATE_FORMAT_COMPRESSED after the pvr_common cleanup is complete.
*/
struct pvr_tex_format_description {

50
src/imagination/vulkan/pvr_job_common.c
View file

@ -51,32 +51,32 @@ void pvr_pbe_get_src_format_and_gamma(VkFormat vk_format,
if (pvr_vk_format_has_32bit_component(vk_format) ||
vk_format_is_int(vk_format)) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (vk_format_is_float(vk_format)) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL;
} else if (vk_format_is_srgb(vk_format)) {
*gamma_out = PVR_PBE_GAMMA_ENABLED;
/* F16 source for gamma'd formats. */
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL;
} else if (vk_format_has_depth(vk_format) &&
vk_format_get_component_bits(vk_format,
UTIL_FORMAT_COLORSPACE_ZS,
0) > 16) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (vk_format_has_stencil(vk_format) &&
vk_format_get_component_bits(vk_format,
UTIL_FORMAT_COLORSPACE_ZS,
1) > 0) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (chan_0_width > 16) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (chan_0_width > 8) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL;
} else if (!with_packed_usc_channel) {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL;
} else {
*src_format_out = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
*src_format_out = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
}
}
@ -144,21 +144,21 @@ void pvr_pbe_pack_state(
switch (surface_params->mem_layout) {
case PVR_MEMLAYOUT_TWIDDLED:
reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_TWIDDLE_2D);
reg.memlayout = ROGUE_PBESTATE_MEMLAYOUT_TWIDDLE_2D;
break;
case PVR_MEMLAYOUT_3DTWIDDLED:
reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_TWIDDLE_3D);
reg.memlayout = ROGUE_PBESTATE_MEMLAYOUT_TWIDDLE_3D;
break;
case PVR_MEMLAYOUT_LINEAR:
default:
reg.memlayout = PVRX(PBESTATE_MEMLAYOUT_LINEAR);
reg.memlayout = ROGUE_PBESTATE_MEMLAYOUT_LINEAR;
break;
}
/* FIXME: Remove rotation and y_flip hardcoding if needed. */
reg.rotation = PVRX(PBESTATE_ROTATION_TYPE_0_DEG);
reg.rotation = ROGUE_PBESTATE_ROTATION_TYPE_0_DEG;
reg.y_flip = false;
/* Note: Due to gamma being overridden above, anything other than
@ -169,11 +169,11 @@ void pvr_pbe_pack_state(
if (surface_params->nr_components == 2)
reg.twocomp_gamma =
PVRX(PBESTATE_TWOCOMP_GAMMA_GAMMA_BOTH_CHANNELS);
ROGUE_PBESTATE_TWOCOMP_GAMMA_GAMMA_BOTH_CHANNELS;
}
reg.linestride = (surface_params->stride - 1) /
PVRX(PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE);
ROGUE_PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE;
reg.minclip_x = render_params->min_x_clip;
/* r, y or depth*/
@ -335,13 +335,13 @@ void pvr_setup_tiles_in_flight(
isp_samples = PVR_GET_FEATURE_VALUE(dev_info, isp_samples_per_pixel, 1);
if (isp_samples == 2) {
if (msaa_mode != PVRX(CR_ISP_AA_MODE_TYPE_AA_NONE))
if (msaa_mode != ROGUE_CR_ISP_AA_MODE_TYPE_AA_NONE)
partition_size *= 2U;
} else if (isp_samples == 4) {
if (msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_4X) ||
msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_8X))
if (msaa_mode == ROGUE_CR_ISP_AA_MODE_TYPE_AA_4X ||
msaa_mode == ROGUE_CR_ISP_AA_MODE_TYPE_AA_8X)
partition_size *= 4U;
else if (msaa_mode == PVRX(CR_ISP_AA_MODE_TYPE_AA_2X))
else if (msaa_mode == ROGUE_CR_ISP_AA_MODE_TYPE_AA_2X)
partition_size *= 2U;
}
@ -466,18 +466,18 @@ void pvr_setup_tiles_in_flight(
pvr_csb_pack (pixel_ctl_out, CR_USC_PIXEL_OUTPUT_CTRL, reg) {
if (pixel_width == 1 && usc_min_output_regs == 1) {
reg.width = PVRX(CR_PIXEL_WIDTH_1REGISTER);
reg.width = ROGUE_CR_PIXEL_WIDTH_1REGISTER;
} else if (pixel_width == 2) {
reg.width = PVRX(CR_PIXEL_WIDTH_2REGISTERS);
reg.width = ROGUE_CR_PIXEL_WIDTH_2REGISTERS;
} else if (pixel_width == 4) {
reg.width = PVRX(CR_PIXEL_WIDTH_4REGISTERS);
reg.width = ROGUE_CR_PIXEL_WIDTH_4REGISTERS;
} else if (pixel_width == 8 &&
PVR_HAS_FEATURE(dev_info, eight_output_registers)) {
reg.width = PVRX(CR_PIXEL_WIDTH_8REGISTERS);
reg.width = ROGUE_CR_PIXEL_WIDTH_8REGISTERS;
} else if (usc_min_output_regs == 1) {
reg.width = PVRX(CR_PIXEL_WIDTH_1REGISTER);
reg.width = ROGUE_CR_PIXEL_WIDTH_1REGISTER;
} else {
reg.width = PVRX(CR_PIXEL_WIDTH_2REGISTERS);
reg.width = ROGUE_CR_PIXEL_WIDTH_2REGISTERS;
}
if (PVR_HAS_FEATURE(dev_info, usc_pixel_partition_mask)) {

8
src/imagination/vulkan/pvr_job_compute.c
View file

@ -83,14 +83,14 @@ pvr_submit_info_stream_init(struct pvr_compute_ctx *ctx,
state.common_shared = true;
state.common_size =
DIV_ROUND_UP(sub_cmd->num_shared_regs << 2,
PVRX(CR_CDM_CONTEXT_PDS1_COMMON_SIZE_UNIT_SIZE));
ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_UNIT_SIZE);
state.temp_size = 0;
assert(load_program_data_size %
PVRX(CR_CDM_CONTEXT_PDS1_DATA_SIZE_UNIT_SIZE) ==
ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_UNIT_SIZE ==
0);
state.data_size =
load_program_data_size / PVRX(CR_CDM_CONTEXT_PDS1_DATA_SIZE_UNIT_SIZE);
load_program_data_size / ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_UNIT_SIZE;
state.fence = false;
}
stream_ptr += pvr_cmd_length(CR_CDM_CONTEXT_PDS1);
@ -169,7 +169,7 @@ static void pvr_submit_info_ext_stream_init(
}
}
if ((*header0_ptr & PVRX(KMD_STREAM_EXTHDR_DATA_MASK)) != 0) {
if ((*header0_ptr & ROGUE_KMD_STREAM_EXTHDR_DATA_MASK) != 0) {
submit_info->fw_stream_len =
(uint8_t *)ext_stream_ptr - (uint8_t *)submit_info->fw_stream;
assert(submit_info->fw_stream_len <= ARRAY_SIZE(submit_info->fw_stream));

72
src/imagination/vulkan/pvr_job_context.c
View file

@ -140,10 +140,10 @@ static VkResult pvr_pds_pt_store_program_create_and_upload(
pvr_gpu_upload_pds(device,
data_buffer,
program.stream_out_terminate_pds_data_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE,
code_buffer,
program.stream_out_terminate_pds_code_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE,
cache_line_size,
pds_upload_out);
@ -213,10 +213,10 @@ static VkResult pvr_pds_pt_resume_program_create_and_upload(
pvr_gpu_upload_pds(device,
data_buffer,
program.stream_out_init_pds_data_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE,
code_buffer,
program.stream_out_init_pds_code_size,
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE),
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE,
cache_line_size,
pds_upload_out);
@ -300,7 +300,7 @@ static void pvr_pds_ctx_sr_program_setup(
pvr_pds_setup_doutu(&program_out->usc_task.usc_task_control,
usc_program_upload_offset,
usc_temps,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
}
@ -318,7 +318,7 @@ static VkResult pvr_pds_render_ctx_sr_program_create_and_upload(
const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
const uint32_t cache_line_size = rogue_get_slc_cache_line_size(dev_info);
const uint32_t pds_data_alignment =
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE / 4U;
/* FIXME: pvr_pds_generate_shared_storing_program() doesn't return the data
* and code size when using the PDS_GENERATE_SIZES mode.
@ -354,10 +354,10 @@ static VkResult pvr_pds_render_ctx_sr_program_create_and_upload(
return pvr_gpu_upload_pds(device,
&staging_buffer[0],
program.data_size,
PVRX(VDMCTRL_PDS_STATE1_PDS_DATA_ADDR_ALIGNMENT),
ROGUE_VDMCTRL_PDS_STATE1_PDS_DATA_ADDR_ALIGNMENT,
&staging_buffer[code_offset],
program.code_size,
PVRX(VDMCTRL_PDS_STATE2_PDS_CODE_ADDR_ALIGNMENT),
ROGUE_VDMCTRL_PDS_STATE2_PDS_CODE_ADDR_ALIGNMENT,
cache_line_size,
pds_upload_out);
}
@ -377,7 +377,7 @@ static VkResult pvr_pds_compute_ctx_sr_program_create_and_upload(
const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
const uint32_t cache_line_size = rogue_get_slc_cache_line_size(dev_info);
const uint32_t pds_data_alignment =
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE / 4U;
/* FIXME: pvr_pds_generate_shared_storing_program() doesn't return the data
* and code size when using the PDS_GENERATE_SIZES mode.
@ -429,20 +429,20 @@ static VkResult pvr_pds_compute_ctx_sr_program_create_and_upload(
assert((uint32_t)(buffer_ptr - staging_buffer) * sizeof(staging_buffer[0]) <
ROGUE_PDS_TASK_PROGRAM_SIZE);
STATIC_ASSERT(PVRX(CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT) ==
PVRX(CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNMENT));
STATIC_ASSERT(ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT ==
ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNMENT);
STATIC_ASSERT(PVRX(CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT) ==
PVRX(CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNMENT));
STATIC_ASSERT(ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT ==
ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNMENT);
return pvr_gpu_upload_pds(
device,
&staging_buffer[0],
program.data_size,
PVRX(CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT),
ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNMENT,
&staging_buffer[code_offset],
(uint32_t)(buffer_ptr - &staging_buffer[code_offset]),
PVRX(CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT),
ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNMENT,
cache_line_size,
pds_upload_out);
}
@ -457,7 +457,7 @@ static VkResult pvr_ctx_sr_programs_setup(struct pvr_device *device,
struct rogue_sr_programs *sr_programs)
{
const uint64_t store_load_state_bo_size =
PVRX(LLS_USC_SHARED_REGS_BUFFER_SIZE) +
ROGUE_LLS_USC_SHARED_REGS_BUFFER_SIZE +
ROGUE_LLS_SHARED_REGS_RESERVE_SIZE;
const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
const uint32_t cache_line_size = rogue_get_slc_cache_line_size(dev_info);
@ -472,7 +472,7 @@ static VkResult pvr_ctx_sr_programs_setup(struct pvr_device *device,
*/
/* 4 blocks (16 dwords / 64 bytes) in USC to prevent fragmentation. */
sr_programs->usc.unified_size =
DIV_ROUND_UP(64, PVRX(VDMCTRL_PDS_STATE0_USC_UNIFIED_SIZE_UNIT_SIZE));
DIV_ROUND_UP(64, ROGUE_VDMCTRL_PDS_STATE0_USC_UNIFIED_SIZE_UNIT_SIZE);
result = pvr_bo_alloc(device,
device->heaps.pds_heap,
@ -708,7 +708,7 @@ static void pvr_render_ctx_switch_fini(struct pvr_device *device,
static void
pvr_rogue_get_vdmctrl_pds_state_words(struct pvr_pds_upload *pds_program,
enum PVRX(VDMCTRL_USC_TARGET) usc_target,
enum ROGUE_VDMCTRL_USC_TARGET usc_target,
uint8_t usc_unified_size,
uint32_t *const state0_out,
uint32_t *const state1_out)
@ -717,22 +717,22 @@ pvr_rogue_get_vdmctrl_pds_state_words(struct pvr_pds_upload *pds_program,
/* Convert the data size from dwords to bytes. */
const uint32_t pds_data_size = PVR_DW_TO_BYTES(pds_program->data_size);
state.dm_target = PVRX(VDMCTRL_DM_TARGET_VDM);
state.dm_target = ROGUE_VDMCTRL_DM_TARGET_VDM;
state.usc_target = usc_target;
state.usc_common_size = 0;
state.usc_unified_size = usc_unified_size;
state.pds_temp_size = 0;
assert(pds_data_size % PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
assert(pds_data_size % ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE ==
0);
state.pds_data_size =
pds_data_size / PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
pds_data_size / ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE;
};
pvr_csb_pack (state1_out, VDMCTRL_PDS_STATE1, state) {
state.pds_data_addr = PVR_DEV_ADDR(pds_program->data_offset);
state.sd_type = PVRX(VDMCTRL_SD_TYPE_PDS);
state.sd_next_type = PVRX(VDMCTRL_SD_TYPE_PDS);
state.sd_type = ROGUE_VDMCTRL_SD_TYPE_PDS;
state.sd_next_type = ROGUE_VDMCTRL_SD_TYPE_PDS;
}
}
@ -748,10 +748,10 @@ pvr_rogue_get_geom_state_stream_out_words(struct pvr_pds_upload *pds_program,
state.sync = true;
assert(pds_data_size %
PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE) ==
ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE ==
0);
state.pds_data_size =
pds_data_size / PVRX(TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE);
pds_data_size / ROGUE_TA_STATE_STREAM_OUT1_PDS_DATA_SIZE_UNIT_SIZE;
state.pds_temp_size = 0;
}
@ -786,7 +786,7 @@ static void pvr_render_ctx_ws_static_state_init(
q_dst = &static_state->geom_state[i].vdm_ctx_store_task0;
pvr_csb_pack (q_dst, CR_VDM_CONTEXT_STORE_TASK0, task0) {
pvr_rogue_get_vdmctrl_pds_state_words(&sr_prog->pds.store_program,
PVRX(VDMCTRL_USC_TARGET_ANY),
ROGUE_VDMCTRL_USC_TARGET_ANY,
sr_prog->usc.unified_size,
&task0.pds_state0,
&task0.pds_state1);
@ -811,7 +811,7 @@ static void pvr_render_ctx_ws_static_state_init(
q_dst = &static_state->geom_state[i].vdm_ctx_resume_task0;
pvr_csb_pack (q_dst, CR_VDM_CONTEXT_RESUME_TASK0, task0) {
pvr_rogue_get_vdmctrl_pds_state_words(&sr_prog->pds.load_program,
PVRX(VDMCTRL_USC_TARGET_ALL),
ROGUE_VDMCTRL_USC_TARGET_ALL,
sr_prog->usc.unified_size,
&task0.pds_state0,
&task0.pds_state1);
@ -867,7 +867,7 @@ VkResult pvr_render_ctx_create(struct pvr_device *device,
result = pvr_bo_alloc(device,
device->heaps.general_heap,
vdm_callstack_size,
PVRX(CR_VDM_CALL_STACK_POINTER_ADDR_ALIGNMENT),
ROGUE_CR_VDM_CALL_STACK_POINTER_ADDR_ALIGNMENT,
0,
&ctx->vdm_callstack_bo);
if (result != VK_SUCCESS)
@ -928,11 +928,11 @@ static VkResult pvr_pds_sr_fence_terminate_program_create_and_upload(
struct pvr_pds_upload *const pds_upload_out)
{
const uint32_t pds_data_alignment =
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) / 4U;
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE / 4U;
const struct pvr_device_runtime_info *dev_runtime_info =
&device->pdevice->dev_runtime_info;
ASSERTED const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
uint32_t staging_buffer[PVRX(PDS_TASK_PROGRAM_SIZE) >> 2U];
uint32_t staging_buffer[ROGUE_PDS_TASK_PROGRAM_SIZE >> 2U];
struct pvr_pds_fence_program program = { 0 };
ASSERTED uint32_t *buffer_end;
uint32_t code_offset;
@ -968,10 +968,10 @@ static VkResult pvr_pds_sr_fence_terminate_program_create_and_upload(
return pvr_gpu_upload_pds(device,
staging_buffer,
data_size,
PVRX(CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNMENT),
ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNMENT,
&staging_buffer[code_offset],
program.code_size,
PVRX(CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNMENT),
ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNMENT,
0,
pds_upload_out);
}
@ -1018,10 +1018,10 @@ static void pvr_compute_ctx_ws_static_state_init(
state.temp_size = 0;
assert(store_program_data_size %
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE ==
0);
state.data_size = store_program_data_size /
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE;
state.fence = true;
}
@ -1054,10 +1054,10 @@ static void pvr_compute_ctx_ws_static_state_init(
state.temp_size = 0;
assert(fence_terminate_program_data_size %
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE) ==
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE ==
0);
state.data_size = fence_terminate_program_data_size /
PVRX(VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE);
ROGUE_VDMCTRL_PDS_STATE0_PDS_DATA_SIZE_UNIT_SIZE;
state.fence = true;
}

54
src/imagination/vulkan/pvr_job_render.c
View file

@ -387,7 +387,7 @@ static VkResult pvr_rt_vheap_rtc_data_init(struct pvr_device *device,
if (layers > 1) {
uint64_t rtc_entries;
vheap_size = ALIGN_POT(vheap_size, PVRX(CR_TA_RTC_ADDR_BASE_ALIGNMENT));
vheap_size = ALIGN_POT(vheap_size, ROGUE_CR_TA_RTC_ADDR_BASE_ALIGNMENT);
rtc_entries = ROGUE_NUM_TEAC + ROGUE_NUM_TE + ROGUE_NUM_VCE;
if (PVR_HAS_QUIRK(&device->pdevice->dev_info, 48545))
@ -398,8 +398,8 @@ static VkResult pvr_rt_vheap_rtc_data_init(struct pvr_device *device,
rtc_size = 0;
}
alignment = MAX2(PVRX(CR_PM_VHEAP_TABLE_BASE_ADDR_ALIGNMENT),
PVRX(CR_TA_RTC_ADDR_BASE_ALIGNMENT));
alignment = MAX2(ROGUE_CR_PM_VHEAP_TABLE_BASE_ADDR_ALIGNMENT,
ROGUE_CR_TA_RTC_ADDR_BASE_ALIGNMENT);
result = pvr_bo_alloc(device,
device->heaps.general_heap,
@ -492,7 +492,7 @@ static VkResult pvr_rt_tpc_data_init(struct pvr_device *device,
return pvr_bo_alloc(device,
device->heaps.general_heap,
tpc_size,
PVRX(CR_TE_TPC_ADDR_BASE_ALIGNMENT),
ROGUE_CR_TE_TPC_ADDR_BASE_ALIGNMENT,
PVR_BO_ALLOC_FLAG_GPU_UNCACHED,
&rt_dataset->tpc_bo);
}
@ -566,12 +566,12 @@ static void pvr_rt_get_region_headers_stride_size(
if (PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format)) {
rgn_headers_size =
ALIGN_POT(rgn_headers_size, PVRX(CR_TE_PSGREGION_ADDR_BASE_ALIGNMENT));
ALIGN_POT(rgn_headers_size, ROGUE_CR_TE_PSGREGION_ADDR_BASE_ALIGNMENT);
}
if (layers > 1) {
rgn_headers_size =
ALIGN_POT(rgn_headers_size, PVRX(CR_TE_PSG_REGION_STRIDE_UNIT_SIZE));
ALIGN_POT(rgn_headers_size, ROGUE_CR_TE_PSG_REGION_STRIDE_UNIT_SIZE);
}
*stride_out = rgn_headers_size;
@ -602,13 +602,13 @@ pvr_rt_mta_mlist_data_init(struct pvr_device *device,
* N is number of RT datas.
*/
rt_datas_mta_size = ALIGN_POT(mta_size * num_rt_datas,
PVRX(CR_PM_MLIST0_BASE_ADDR_ALIGNMENT));
ROGUE_CR_PM_MLIST0_BASE_ADDR_ALIGNMENT);
rt_datas_mlist_size = mlist_size * num_rt_datas;
result = pvr_bo_alloc(device,
device->heaps.general_heap,
rt_datas_mta_size + rt_datas_mlist_size,
PVRX(CR_PM_MTILE_ARRAY_BASE_ADDR_ALIGNMENT),
ROGUE_CR_PM_MTILE_ARRAY_BASE_ADDR_ALIGNMENT,
PVR_BO_ALLOC_FLAG_GPU_UNCACHED,
&rt_dataset->mta_mlist_bo);
if (result != VK_SUCCESS)
@ -671,7 +671,7 @@ pvr_rt_rgn_headers_data_init(struct pvr_device *device,
result = pvr_bo_alloc(device,
device->heaps.rgn_hdr_heap,
rgn_headers_size * num_rt_datas,
PVRX(CR_TE_PSGREGION_ADDR_BASE_ALIGNMENT),
ROGUE_CR_TE_PSGREGION_ADDR_BASE_ALIGNMENT,
PVR_BO_ALLOC_FLAG_GPU_UNCACHED,
&rt_dataset->rgn_headers_bo);
if (result != VK_SUCCESS)
@ -966,7 +966,7 @@ static void pvr_geom_state_stream_init(struct pvr_render_ctx *ctx,
value.completeonterminate = job->geometry_terminate;
value.region_stride = job->rt_dataset->rgn_headers_stride /
PVRX(CR_TE_PSG_REGION_STRIDE_UNIT_SIZE);
ROGUE_CR_TE_PSG_REGION_STRIDE_UNIT_SIZE;
value.forcenewstate = PVR_HAS_QUIRK(dev_info, 52942);
}
@ -982,7 +982,7 @@ static void pvr_geom_state_stream_init(struct pvr_render_ctx *ctx,
value.usc_common_size =
DIV_ROUND_UP(shared_registers_size,
PVRX(VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE));
ROGUE_VDMCTRL_PDS_STATE0_USC_COMMON_SIZE_UNIT_SIZE);
}
stream_ptr += pvr_cmd_length(VDMCTRL_PDS_STATE0);
@ -1029,7 +1029,7 @@ pvr_geom_state_stream_ext_init(struct pvr_render_ctx *ctx,
}
}
if ((*header0_ptr & PVRX(KMD_STREAM_EXTHDR_DATA_MASK)) != 0) {
if ((*header0_ptr & ROGUE_KMD_STREAM_EXTHDR_DATA_MASK) != 0) {
state->fw_stream_len =
(uint8_t *)ext_stream_ptr - (uint8_t *)state->fw_stream;
assert(state->fw_stream_len <= ARRAY_SIZE(state->fw_stream));
@ -1092,7 +1092,7 @@ static inline uint32_t pvr_frag_km_stream_pds_eot_data_addr_offset(
offset += pvr_cmd_length(CR_TPU_BORDER_COLOUR_TABLE_PDM);
offset += ROGUE_NUM_CR_PDS_BGRND_WORDS * DWORDS_PER_U64;
offset += ROGUE_NUM_CR_PDS_BGRND_WORDS * DWORDS_PER_U64;
offset += PVRX(KMD_STREAM_USC_CLEAR_REGISTER_COUNT) *
offset += ROGUE_KMD_STREAM_USC_CLEAR_REGISTER_COUNT *
pvr_cmd_length(CR_USC_CLEAR_REGISTER);
offset += pvr_cmd_length(CR_USC_PIXEL_OUTPUT_CTRL);
offset += pvr_cmd_length(CR_ISP_BGOBJDEPTH);
@ -1118,10 +1118,10 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
const struct pvr_device_runtime_info *dev_runtime_info =
&pdevice->dev_runtime_info;
const struct pvr_device_info *dev_info = &pdevice->dev_info;
const enum PVRX(CR_ISP_AA_MODE_TYPE)
isp_aa_mode = pvr_cr_isp_aa_mode_type(job->samples);
const enum ROGUE_CR_ISP_AA_MODE_TYPE isp_aa_mode =
pvr_cr_isp_aa_mode_type(job->samples);
enum PVRX(CR_ZLS_FORMAT_TYPE) zload_format = PVRX(CR_ZLS_FORMAT_TYPE_F32Z);
enum ROGUE_CR_ZLS_FORMAT_TYPE zload_format = ROGUE_CR_ZLS_FORMAT_TYPE_F32Z;
uint32_t *stream_ptr = (uint32_t *)state->fw_stream;
uint32_t *stream_len_ptr = stream_ptr;
uint32_t pixel_ctl;
@ -1236,8 +1236,8 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
* values.
*/
pvr_csb_pack ((uint64_t *)stream_ptr, CR_FB_CDC_ZLS, value) {
value.fbdc_depth_fmt = PVRX(TEXSTATE_FORMAT_F32);
value.fbdc_stencil_fmt = PVRX(TEXSTATE_FORMAT_U8);
value.fbdc_depth_fmt = ROGUE_TEXSTATE_FORMAT_F32;
value.fbdc_stencil_fmt = ROGUE_TEXSTATE_FORMAT_U8;
}
stream_ptr += pvr_cmd_length(CR_FB_CDC_ZLS);
}
@ -1284,9 +1284,9 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
memset(stream_ptr,
0,
PVRX(KMD_STREAM_USC_CLEAR_REGISTER_COUNT) *
ROGUE_KMD_STREAM_USC_CLEAR_REGISTER_COUNT *
PVR_DW_TO_BYTES(pvr_cmd_length(CR_USC_CLEAR_REGISTER)));
stream_ptr += PVRX(KMD_STREAM_USC_CLEAR_REGISTER_COUNT) *
stream_ptr += ROGUE_KMD_STREAM_USC_CLEAR_REGISTER_COUNT *
pvr_cmd_length(CR_USC_CLEAR_REGISTER);
*stream_ptr = pixel_ctl;
@ -1300,15 +1300,15 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
* - job->depth_clear_value is set to a sensible default in that case.
*/
switch (zload_format) {
case PVRX(CR_ZLS_FORMAT_TYPE_F32Z):
case ROGUE_CR_ZLS_FORMAT_TYPE_F32Z:
value.value = fui(depth_clear);
break;
case PVRX(CR_ZLS_FORMAT_TYPE_16BITINT):
case ROGUE_CR_ZLS_FORMAT_TYPE_16BITINT:
value.value = _mesa_float_to_unorm(depth_clear, 16);
break;
case PVRX(CR_ZLS_FORMAT_TYPE_24BITINT):
case ROGUE_CR_ZLS_FORMAT_TYPE_24BITINT:
value.value = _mesa_float_to_unorm(depth_clear, 24);
break;
@ -1353,11 +1353,11 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
pvr_csb_pack (stream_ptr, CR_EVENT_PIXEL_PDS_INFO, value) {
value.const_size =
DIV_ROUND_UP(ctx->device->pixel_event_data_size_in_dwords,
PVRX(CR_EVENT_PIXEL_PDS_INFO_CONST_SIZE_UNIT_SIZE));
ROGUE_CR_EVENT_PIXEL_PDS_INFO_CONST_SIZE_UNIT_SIZE);
value.temp_stride = 0;
value.usc_sr_size =
DIV_ROUND_UP(PVR_STATE_PBE_DWORDS,
PVRX(CR_EVENT_PIXEL_PDS_INFO_USC_SR_SIZE_UNIT_SIZE));
ROGUE_CR_EVENT_PIXEL_PDS_INFO_USC_SR_SIZE_UNIT_SIZE);
}
stream_ptr += pvr_cmd_length(CR_EVENT_PIXEL_PDS_INFO);
@ -1376,7 +1376,7 @@ static void pvr_frag_state_stream_init(struct pvr_render_ctx *ctx,
*/
if (PVR_HAS_FEATURE(dev_info, slc_mcu_cache_controls) &&
dev_runtime_info->num_phantoms > 1 && job->frag_uses_atomic_ops) {
value.phantom_0 = PVRX(KMD_STREAM_PIXEL_PHANTOM_STATE_ENABLED);
value.phantom_0 = ROGUE_KMD_STREAM_PIXEL_PHANTOM_STATE_ENABLED;
}
}
stream_ptr += pvr_cmd_length(KMD_STREAM_PIXEL_PHANTOM);
@ -1475,7 +1475,7 @@ pvr_frag_state_stream_ext_init(struct pvr_render_ctx *ctx,
}
}
if ((*header0_ptr & PVRX(KMD_STREAM_EXTHDR_DATA_MASK)) != 0) {
if ((*header0_ptr & ROGUE_KMD_STREAM_EXTHDR_DATA_MASK) != 0) {
state->fw_stream_len =
(uint8_t *)ext_stream_ptr - (uint8_t *)state->fw_stream;
assert(state->fw_stream_len <= ARRAY_SIZE(state->fw_stream));

2
src/imagination/vulkan/pvr_job_render.h
View file

@ -110,7 +110,7 @@ struct pvr_render_job {
uint32_t height;
VkExtent2D physical_extent;
uint32_t layer_size;
enum PVRX(CR_ZLS_FORMAT_TYPE) zls_format;
enum ROGUE_CR_ZLS_FORMAT_TYPE zls_format;
/* FIXME: This should be of type 'enum pvr_memlayout', but this is defined
* in pvr_private.h, which causes a circular include dependency. For now,
* treat it as a uint32_t. A couple of ways to possibly fix this:

296
src/imagination/vulkan/pvr_job_transfer.c
View file

@ -583,18 +583,18 @@ static inline void pvr_setup_hwbg_object(const struct pvr_device_info *dev_info,
reg.shader_addr = PVR_DEV_ADDR(state->pds_shader_task_offset);
assert(pvr_dev_addr_is_aligned(
reg.shader_addr,
PVRX(CR_PDS_BGRND0_BASE_SHADER_ADDR_ALIGNMENT)));
ROGUE_CR_PDS_BGRND0_BASE_SHADER_ADDR_ALIGNMENT));
reg.texunicode_addr = PVR_DEV_ADDR(state->uni_tex_code_offset);
assert(pvr_dev_addr_is_aligned(
reg.texunicode_addr,
PVRX(CR_PDS_BGRND0_BASE_TEXUNICODE_ADDR_ALIGNMENT)));
ROGUE_CR_PDS_BGRND0_BASE_TEXUNICODE_ADDR_ALIGNMENT));
}
pvr_csb_pack (&regs->pds_bgnd1_base, CR_PDS_BGRND1_BASE, reg) {
reg.texturedata_addr = PVR_DEV_ADDR(state->tex_state_data_offset);
assert(pvr_dev_addr_is_aligned(
reg.texturedata_addr,
PVRX(CR_PDS_BGRND1_BASE_TEXTUREDATA_ADDR_ALIGNMENT)));
ROGUE_CR_PDS_BGRND1_BASE_TEXTUREDATA_ADDR_ALIGNMENT));
}
/* BGRND 2 not needed, background object PDS doesn't use uniform program. */
@ -602,24 +602,24 @@ static inline void pvr_setup_hwbg_object(const struct pvr_device_info *dev_info,
pvr_csb_pack (&regs->pds_bgnd3_sizeinfo, CR_PDS_BGRND3_SIZEINFO, reg) {
reg.usc_sharedsize =
DIV_ROUND_UP(state->common_ptr,
PVRX(CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE);
assert(!(state->uniform_data_size &
(PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_UNIFORMSIZE_UNIT_SIZE) - 1)));
(ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_UNIFORMSIZE_UNIT_SIZE - 1)));
reg.pds_uniformsize =
state->uniform_data_size /
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_UNIFORMSIZE_UNIT_SIZE);
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_UNIFORMSIZE_UNIT_SIZE;
assert(
!(state->tex_state_data_size &
(PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE) - 1)));
(ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE - 1)));
reg.pds_texturestatesize =
state->tex_state_data_size /
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE);
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE;
reg.pds_tempsize =
DIV_ROUND_UP(state->pds_temps,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE);
}
}
@ -636,13 +636,13 @@ pvr_is_surface_aligned(pvr_dev_addr_t dev_addr, bool is_input, uint32_t bpp)
if (is_input) {
if ((dev_addr.addr &
(PVRX(TEXSTATE_STRIDE_IMAGE_WORD1_TEXADDR_ALIGNMENT) - 1U)) !=
(ROGUE_TEXSTATE_STRIDE_IMAGE_WORD1_TEXADDR_ALIGNMENT - 1U)) !=
0ULL) {
return false;
}
} else {
if ((dev_addr.addr &
(PVRX(PBESTATE_STATE_WORD0_ADDRESS_LOW_ALIGNMENT) - 1U)) != 0ULL) {
(ROGUE_PBESTATE_STATE_WORD0_ADDRESS_LOW_ALIGNMENT - 1U)) != 0ULL) {
return false;
}
}
@ -981,14 +981,14 @@ static void pvr_pbe_setup_swizzle(const struct pvr_transfer_cmd *transfer_cmd,
dst->vk_format == VK_FORMAT_R8G8B8A8_UNORM ||
dst->vk_format == VK_FORMAT_A8B8G8R8_UNORM_PACK32)) {
surf_params->source_format =
PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (state->shader_props.layer_props.pbe_format ==
PVR_TRANSFER_PBE_PIXEL_SRC_F16_U8) {
surf_params->source_format =
PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL);
ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL;
} else if (red_width <= 8U) {
surf_params->source_format =
PVRX(PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL);
ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL;
}
} else if (red_width == 32U && !state->dont_force_pbe) {
uint32_t count = 0U;
@ -1094,7 +1094,7 @@ static VkResult pvr_pbe_setup_emit(const struct pvr_transfer_cmd *transfer_cmd,
pvr_pds_setup_doutu(&program.task_control,
addr.addr,
0U,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_set_sizes_pixel_event(&program, dev_info);
@ -1125,11 +1125,11 @@ static VkResult pvr_pbe_setup_emit(const struct pvr_transfer_cmd *transfer_cmd,
pvr_cmd_buffer_upload_pds(transfer_cmd->cmd_buffer,
staging_buffer,
program.data_size,
PVRX(CR_EVENT_PIXEL_PDS_DATA_ADDR_ALIGNMENT),
ROGUE_CR_EVENT_PIXEL_PDS_DATA_ADDR_ALIGNMENT,
staging_buffer + program.data_size,
program.code_size,
PVRX(CR_EVENT_PIXEL_PDS_CODE_ADDR_ALIGNMENT),
PVRX(CR_EVENT_PIXEL_PDS_DATA_ADDR_ALIGNMENT),
ROGUE_CR_EVENT_PIXEL_PDS_CODE_ADDR_ALIGNMENT,
ROGUE_CR_EVENT_PIXEL_PDS_DATA_ADDR_ALIGNMENT,
&pds_upload);
vk_free(&device->vk.alloc, staging_buffer);
if (result != VK_SUCCESS)
@ -1139,10 +1139,10 @@ static VkResult pvr_pbe_setup_emit(const struct pvr_transfer_cmd *transfer_cmd,
reg.temp_stride = 0U;
reg.const_size =
DIV_ROUND_UP(program.data_size,
PVRX(CR_EVENT_PIXEL_PDS_INFO_CONST_SIZE_UNIT_SIZE));
ROGUE_CR_EVENT_PIXEL_PDS_INFO_CONST_SIZE_UNIT_SIZE);
reg.usc_sr_size =
DIV_ROUND_UP(rt_count * PVR_STATE_PBE_DWORDS,
PVRX(CR_EVENT_PIXEL_PDS_INFO_USC_SR_SIZE_UNIT_SIZE));
ROGUE_CR_EVENT_PIXEL_PDS_INFO_USC_SR_SIZE_UNIT_SIZE);
}
pvr_csb_pack (&regs->event_pixel_pds_data, CR_EVENT_PIXEL_PDS_DATA, reg) {
@ -1233,7 +1233,7 @@ static VkResult pvr_pbe_setup(const struct pvr_transfer_cmd *transfer_cmd,
if (PVR_HAS_FEATURE(dev_info, paired_tiles)) {
if (pbe_regs[2U] &
(1ULL << PVRX(PBESTATE_REG_WORD2_PAIR_TILES_SHIFT))) {
(1ULL << ROGUE_PBESTATE_REG_WORD2_PAIR_TILES_SHIFT)) {
if (transfer_cmd->dst.mem_layout == PVR_MEMLAYOUT_TWIDDLED)
state->pair_tiles = PVR_PAIRED_TILES_Y;
else
@ -1485,28 +1485,28 @@ static VkResult pvr_sampler_state_for_surface(
uint64_t sampler_state[2U] = { 0UL, 0UL };
pvr_csb_pack (&sampler_state[0U], TEXSTATE_SAMPLER, reg) {
reg.anisoctl = PVRX(TEXSTATE_ANISOCTL_DISABLED);
reg.minlod = PVRX(TEXSTATE_CLAMP_MIN);
reg.maxlod = PVRX(TEXSTATE_CLAMP_MIN);
reg.dadjust = PVRX(TEXSTATE_DADJUST_MIN_UINT);
reg.anisoctl = ROGUE_TEXSTATE_ANISOCTL_DISABLED;
reg.minlod = ROGUE_TEXSTATE_CLAMP_MIN;
reg.maxlod = ROGUE_TEXSTATE_CLAMP_MIN;
reg.dadjust = ROGUE_TEXSTATE_DADJUST_MIN_UINT;
if (filter == PVR_FILTER_DONTCARE || filter == PVR_FILTER_POINT) {
reg.minfilter = PVRX(TEXSTATE_FILTER_POINT);
reg.magfilter = PVRX(TEXSTATE_FILTER_POINT);
reg.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
reg.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
} else if (filter == PVR_FILTER_LINEAR) {
reg.minfilter = PVRX(TEXSTATE_FILTER_LINEAR);
reg.magfilter = PVRX(TEXSTATE_FILTER_LINEAR);
reg.minfilter = ROGUE_TEXSTATE_FILTER_LINEAR;
reg.magfilter = ROGUE_TEXSTATE_FILTER_LINEAR;
} else {
assert(PVR_HAS_FEATURE(dev_info, tf_bicubic_filter));
reg.minfilter = PVRX(TEXSTATE_FILTER_BICUBIC);
reg.magfilter = PVRX(TEXSTATE_FILTER_BICUBIC);
reg.minfilter = ROGUE_TEXSTATE_FILTER_BICUBIC;
reg.magfilter = ROGUE_TEXSTATE_FILTER_BICUBIC;
}
reg.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
reg.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
if (surface->mem_layout == PVR_MEMLAYOUT_3DTWIDDLED)
reg.addrmode_w = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.addrmode_w = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
}
assert(sampler < PVR_TRANSFER_MAX_IMAGES);
@ -2101,7 +2101,7 @@ pvr_pds_unitex(const struct pvr_device_info *dev_info,
pvr_pds_set_sizes_pixel_shader_sa_texture_data(program, dev_info);
state->tex_state_data_size =
ALIGN_POT(program->data_size,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE);
result =
pvr_cmd_buffer_alloc_mem(transfer_cmd->cmd_buffer,
@ -2241,13 +2241,13 @@ static VkResult pvr_pack_clear_color(VkFormat format,
uint32_t pbe_pack_mode = pvr_get_pbe_packmode(format);
const bool pbe_norm = pvr_vk_format_is_fully_normalized(format);
if (pbe_pack_mode == PVRX(PBESTATE_PACKMODE_INVALID))
if (pbe_pack_mode == ROGUE_PBESTATE_PACKMODE_INVALID)
return vk_error(NULL, VK_ERROR_FORMAT_NOT_SUPPORTED);
/* Set packed color based on PBE pack mode and PBE norm. */
switch (pbe_pack_mode) {
case PVRX(PBESTATE_PACKMODE_U8U8U8U8):
case PVRX(PBESTATE_PACKMODE_A8R3G3B2):
case ROGUE_PBESTATE_PACKMODE_U8U8U8U8:
case ROGUE_PBESTATE_PACKMODE_A8R3G3B2:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 8) & 0xFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 8) & 0xFFU) << 8;
@ -2261,9 +2261,9 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S8S8S8S8):
case PVRX(PBESTATE_PACKMODE_X8U8S8S8):
case PVRX(PBESTATE_PACKMODE_X8S8S8U8):
case ROGUE_PBESTATE_PACKMODE_S8S8S8S8:
case ROGUE_PBESTATE_PACKMODE_X8U8S8S8:
case ROGUE_PBESTATE_PACKMODE_X8S8S8U8:
if (pbe_norm) {
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, false);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, false) << 16;
@ -2277,7 +2277,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_U16U16U16U16):
case ROGUE_PBESTATE_PACKMODE_U16U16U16U16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2291,7 +2291,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S16S16S16S16):
case ROGUE_PBESTATE_PACKMODE_S16S16S16S16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_sfixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2305,14 +2305,14 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_A2_XRBIAS_U10U10U10):
case PVRX(PBESTATE_PACKMODE_ARGBV16_XR10):
case PVRX(PBESTATE_PACKMODE_F16F16F16F16):
case PVRX(PBESTATE_PACKMODE_A2R10B10G10):
case PVRX(PBESTATE_PACKMODE_A4R4G4B4):
case PVRX(PBESTATE_PACKMODE_A1R5G5B5):
case PVRX(PBESTATE_PACKMODE_R5G5B5A1):
case PVRX(PBESTATE_PACKMODE_R5G6B5):
case ROGUE_PBESTATE_PACKMODE_A2_XRBIAS_U10U10U10:
case ROGUE_PBESTATE_PACKMODE_ARGBV16_XR10:
case ROGUE_PBESTATE_PACKMODE_F16F16F16F16:
case ROGUE_PBESTATE_PACKMODE_A2R10B10G10:
case ROGUE_PBESTATE_PACKMODE_A4R4G4B4:
case ROGUE_PBESTATE_PACKMODE_A1R5G5B5:
case ROGUE_PBESTATE_PACKMODE_R5G5B5A1:
case ROGUE_PBESTATE_PACKMODE_R5G6B5:
if (red_width > 0) {
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, false);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, false) << 16;
@ -2324,25 +2324,25 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_U32U32U32U32):
case ROGUE_PBESTATE_PACKMODE_U32U32U32U32:
pkd_color[0] = color[0].ui;
pkd_color[1] = color[1].ui;
pkd_color[2] = color[2].ui;
pkd_color[3] = color[3].ui;
break;
case PVRX(PBESTATE_PACKMODE_S32S32S32S32):
case ROGUE_PBESTATE_PACKMODE_S32S32S32S32:
pkd_color[0] = (uint32_t)color[0].i;
pkd_color[1] = (uint32_t)color[1].i;
pkd_color[2] = (uint32_t)color[2].i;
pkd_color[3] = (uint32_t)color[3].i;
break;
case PVRX(PBESTATE_PACKMODE_F32F32F32F32):
case ROGUE_PBESTATE_PACKMODE_F32F32F32F32:
memcpy(pkd_color, &color[0].f, 4U * sizeof(float));
break;
case PVRX(PBESTATE_PACKMODE_R10B10G10A2):
case ROGUE_PBESTATE_PACKMODE_R10B10G10A2:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 10) & 0xFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 10) & 0xFFU) << 10;
@ -2362,16 +2362,16 @@ static VkResult pvr_pack_clear_color(VkFormat format,
break;
case PVRX(PBESTATE_PACKMODE_A2F10F10F10):
case PVRX(PBESTATE_PACKMODE_F10F10F10A2):
case ROGUE_PBESTATE_PACKMODE_A2F10F10F10:
case ROGUE_PBESTATE_PACKMODE_F10F10F10A2:
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 10) & 0xFFU;
pkd_color[0] |= (pvr_float_to_sfixed(color[1].f, 10) & 0xFFU) << 10;
pkd_color[0] |= (pvr_float_to_sfixed(color[2].f, 10) & 0xFFU) << 20;
pkd_color[0] |= (pvr_float_to_sfixed(color[3].f, 2) & 0xFFU) << 30;
break;
case PVRX(PBESTATE_PACKMODE_U8U8U8):
case PVRX(PBESTATE_PACKMODE_R5SG5SB6):
case ROGUE_PBESTATE_PACKMODE_U8U8U8:
case ROGUE_PBESTATE_PACKMODE_R5SG5SB6:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 8) & 0xFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 8) & 0xFFU) << 8;
@ -2383,8 +2383,8 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S8S8S8):
case PVRX(PBESTATE_PACKMODE_B6G5SR5S):
case ROGUE_PBESTATE_PACKMODE_S8S8S8:
case ROGUE_PBESTATE_PACKMODE_B6G5SR5S:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 8) & 0xFFU;
pkd_color[0] |= (pvr_float_to_sfixed(color[1].f, 8) & 0xFFU) << 8;
@ -2396,7 +2396,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_U16U16U16):
case ROGUE_PBESTATE_PACKMODE_U16U16U16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2408,7 +2408,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S16S16S16):
case ROGUE_PBESTATE_PACKMODE_S16S16S16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_sfixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2420,37 +2420,37 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_F16F16F16):
case PVRX(PBESTATE_PACKMODE_F11F11F10):
case PVRX(PBESTATE_PACKMODE_F10F11F11):
case PVRX(PBESTATE_PACKMODE_SE9995):
case ROGUE_PBESTATE_PACKMODE_F16F16F16:
case ROGUE_PBESTATE_PACKMODE_F11F11F10:
case ROGUE_PBESTATE_PACKMODE_F10F11F11:
case ROGUE_PBESTATE_PACKMODE_SE9995:
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, true);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, true) << 16;
pkd_color[1] = (uint32_t)pvr_float_to_f16(color[2].f, true);
break;
case PVRX(PBESTATE_PACKMODE_U32U32U32):
case ROGUE_PBESTATE_PACKMODE_U32U32U32:
pkd_color[0] = color[0].ui;
pkd_color[1] = color[1].ui;
pkd_color[2] = color[2].ui;
break;
case PVRX(PBESTATE_PACKMODE_S32S32S32):
case ROGUE_PBESTATE_PACKMODE_S32S32S32:
pkd_color[0] = (uint32_t)color[0].i;
pkd_color[1] = (uint32_t)color[1].i;
pkd_color[2] = (uint32_t)color[2].i;
break;
case PVRX(PBESTATE_PACKMODE_X24G8X32):
case PVRX(PBESTATE_PACKMODE_U8X24):
case ROGUE_PBESTATE_PACKMODE_X24G8X32:
case ROGUE_PBESTATE_PACKMODE_U8X24:
pkd_color[1] = (color[1].ui & 0xFFU) << 24;
break;
case PVRX(PBESTATE_PACKMODE_F32F32F32):
case ROGUE_PBESTATE_PACKMODE_F32F32F32:
memcpy(pkd_color, &color[0].f, 3U * sizeof(float));
break;
case PVRX(PBESTATE_PACKMODE_U8U8):
case ROGUE_PBESTATE_PACKMODE_U8U8:
if (pbe_norm) {
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, false);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, false) << 16;
@ -2460,7 +2460,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S8S8):
case ROGUE_PBESTATE_PACKMODE_S8S8:
if (pbe_norm) {
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, false);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, false) << 16;
@ -2472,7 +2472,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_U16U16):
case ROGUE_PBESTATE_PACKMODE_U16U16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_ufixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2482,7 +2482,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_S16S16):
case ROGUE_PBESTATE_PACKMODE_S16S16:
if (pbe_norm) {
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 16) & 0xFFFFU;
pkd_color[0] |= (pvr_float_to_sfixed(color[1].f, 16) & 0xFFFFU) << 16;
@ -2492,37 +2492,37 @@ static VkResult pvr_pack_clear_color(VkFormat format,
}
break;
case PVRX(PBESTATE_PACKMODE_F16F16):
case ROGUE_PBESTATE_PACKMODE_F16F16:
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, true);
pkd_color[0] |= (uint32_t)pvr_float_to_f16(color[1].f, true) << 16;
break;
case PVRX(PBESTATE_PACKMODE_U32U32):
case ROGUE_PBESTATE_PACKMODE_U32U32:
pkd_color[0] = color[0].ui;
pkd_color[1] = color[1].ui;
break;
case PVRX(PBESTATE_PACKMODE_S32S32):
case ROGUE_PBESTATE_PACKMODE_S32S32:
pkd_color[0] = (uint32_t)color[0].i;
pkd_color[1] = (uint32_t)color[1].i;
break;
case PVRX(PBESTATE_PACKMODE_X24U8F32):
case PVRX(PBESTATE_PACKMODE_X24X8F32):
case ROGUE_PBESTATE_PACKMODE_X24U8F32:
case ROGUE_PBESTATE_PACKMODE_X24X8F32:
memcpy(pkd_color, &color[0].f, 1U * sizeof(float));
pkd_color[1] = color[1].ui & 0xFFU;
break;
case PVRX(PBESTATE_PACKMODE_F32F32):
case ROGUE_PBESTATE_PACKMODE_F32F32:
memcpy(pkd_color, &color[0].f, 2U * sizeof(float));
break;
case PVRX(PBESTATE_PACKMODE_ST8U24):
case ROGUE_PBESTATE_PACKMODE_ST8U24:
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 24) & 0xFFFFFFU;
pkd_color[0] |= color[1].ui << 24;
break;
case PVRX(PBESTATE_PACKMODE_U8):
case ROGUE_PBESTATE_PACKMODE_U8:
if (format == VK_FORMAT_S8_UINT)
pkd_color[0] = color[1].ui & 0xFFU;
else if (pbe_norm)
@ -2532,33 +2532,33 @@ static VkResult pvr_pack_clear_color(VkFormat format,
break;
case PVRX(PBESTATE_PACKMODE_S8):
case ROGUE_PBESTATE_PACKMODE_S8:
if (pbe_norm)
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, false);
else
pkd_color[0] = color[0].ui & 0xFFU;
break;
case PVRX(PBESTATE_PACKMODE_U16):
case ROGUE_PBESTATE_PACKMODE_U16:
if (pbe_norm)
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 16) & 0xFFFFU;
else
pkd_color[0] = color[0].ui & 0xFFFFU;
break;
case PVRX(PBESTATE_PACKMODE_S16):
case ROGUE_PBESTATE_PACKMODE_S16:
if (pbe_norm)
pkd_color[0] = pvr_float_to_sfixed(color[0].f, 16) & 0xFFFFU;
else
pkd_color[0] = color[0].ui & 0xFFFFU;
break;
case PVRX(PBESTATE_PACKMODE_F16):
case ROGUE_PBESTATE_PACKMODE_F16:
pkd_color[0] = (uint32_t)pvr_float_to_f16(color[0].f, true);
break;
/* U32 */
case PVRX(PBESTATE_PACKMODE_U32):
case ROGUE_PBESTATE_PACKMODE_U32:
if (format == VK_FORMAT_X8_D24_UNORM_PACK32) {
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 24) & 0xFFFFFFU;
} else if (format == VK_FORMAT_D24_UNORM_S8_UINT) {
@ -2575,23 +2575,23 @@ static VkResult pvr_pack_clear_color(VkFormat format,
break;
/* U24ST8 */
case PVRX(PBESTATE_PACKMODE_U24ST8):
case ROGUE_PBESTATE_PACKMODE_U24ST8:
pkd_color[1] = (color[1].ui & 0xFFU) << 24;
pkd_color[1] |= pvr_float_to_ufixed(color[0].f, 24) & 0xFFFFFFU;
break;
/* S32 */
case PVRX(PBESTATE_PACKMODE_S32):
case ROGUE_PBESTATE_PACKMODE_S32:
pkd_color[0] = (uint32_t)color[0].i;
break;
/* F32 */
case PVRX(PBESTATE_PACKMODE_F32):
case ROGUE_PBESTATE_PACKMODE_F32:
memcpy(pkd_color, &color[0].f, sizeof(float));
break;
/* X8U24 */
case PVRX(PBESTATE_PACKMODE_X8U24):
case ROGUE_PBESTATE_PACKMODE_X8U24:
pkd_color[0] = pvr_float_to_ufixed(color[0].f, 24) & 0xFFFFFFU;
break;
@ -2605,7 +2605,7 @@ static VkResult pvr_pack_clear_color(VkFormat format,
static VkResult
pvr_isp_scan_direction(struct pvr_transfer_cmd *transfer_cmd,
bool custom_mapping,
enum PVRX(CR_DIR_TYPE) *const dir_type_out)
enum ROGUE_CR_DIR_TYPE *const dir_type_out)
{
pvr_dev_addr_t dst_dev_addr = transfer_cmd->dst.dev_addr;
bool backwards_in_x = false;
@ -2652,14 +2652,14 @@ pvr_isp_scan_direction(struct pvr_transfer_cmd *transfer_cmd,
if (backwards_in_x) {
if (backwards_in_y)
*dir_type_out = PVRX(CR_DIR_TYPE_BR2TL);
*dir_type_out = ROGUE_CR_DIR_TYPE_BR2TL;
else
*dir_type_out = PVRX(CR_DIR_TYPE_TR2BL);
*dir_type_out = ROGUE_CR_DIR_TYPE_TR2BL;
} else {
if (backwards_in_y)
*dir_type_out = PVRX(CR_DIR_TYPE_BL2TR);
*dir_type_out = ROGUE_CR_DIR_TYPE_BL2TR;
else
*dir_type_out = PVRX(CR_DIR_TYPE_TL2BR);
*dir_type_out = ROGUE_CR_DIR_TYPE_TL2BR;
}
return VK_SUCCESS;
@ -2883,7 +2883,7 @@ static VkResult pvr_3d_copy_blit_core(struct pvr_transfer_ctx *ctx,
pvr_setup_hwbg_object(dev_info, state);
pvr_csb_pack (&regs->isp_render, CR_ISP_RENDER, reg) {
reg.mode_type = PVRX(CR_ISP_RENDER_MODE_TYPE_FAST_SCALE);
reg.mode_type = ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_SCALE;
result = pvr_isp_scan_direction(transfer_cmd,
state->custom_mapping.pass_count,
@ -2963,9 +2963,9 @@ pvr_pds_coeff_task(struct pvr_transfer_ctx *ctx,
PDSINST_DOUT_FIELDS_DOUTI_SRC,
reg) {
if (sample_3d)
reg.size = PVRX(PDSINST_DOUTI_SIZE_3D);
reg.size = ROGUE_PDSINST_DOUTI_SIZE_3D;
else
reg.size = PVRX(PDSINST_DOUTI_SIZE_2D);
reg.size = ROGUE_PDSINST_DOUTI_SIZE_2D;
reg.perspective = false;
@ -2980,7 +2980,7 @@ pvr_pds_coeff_task(struct pvr_transfer_ctx *ctx,
* l1 U <= offs 4
* ...
*/
reg.shademodel = PVRX(PDSINST_DOUTI_SHADEMODEL_GOURUAD);
reg.shademodel = ROGUE_PDSINST_DOUTI_SHADEMODEL_GOURUAD;
reg.f32_offset = 0U;
}
@ -3225,25 +3225,25 @@ static void pvr_isp_prim_block_pds_state(const struct pvr_device_info *dev_info,
pvr_csb_pack (cs_ptr, TA_STATE_PDS_SIZEINFO1, info1) {
info1.pds_uniformsize =
state->uniform_data_size /
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_UNIFORMSIZE_UNIT_SIZE;
info1.pds_texturestatesize =
state->tex_state_data_size /
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE;
info1.pds_varyingsize =
state->coeff_data_size /
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_VARYINGSIZE_UNIT_SIZE;
info1.usc_varyingsize =
ALIGN_POT(state->usc_coeff_regs,
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE)) /
PVRX(TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE) /
ROGUE_TA_STATE_PDS_SIZEINFO1_USC_VARYINGSIZE_UNIT_SIZE;
info1.pds_tempsize =
ALIGN_POT(state->pds_temps,
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE)) /
PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE) /
ROGUE_TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE;
}
cs_ptr++;
@ -3266,8 +3266,8 @@ static void pvr_isp_prim_block_pds_state(const struct pvr_device_info *dev_info,
pvr_csb_pack (cs_ptr, TA_STATE_PDS_SIZEINFO2, info) {
info.usc_sharedsize =
ALIGN_POT(state->common_ptr,
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE)) /
PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE);
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE) /
ROGUE_TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE;
info.pds_tri_merge_disable = !PVR_HAS_ERN(dev_info, 42307);
info.pds_batchnum = 0U;
}
@ -3319,10 +3319,10 @@ static void pvr_isp_prim_block_isp_state(const struct pvr_device_info *dev_info,
cs_ptr += pvr_cmd_length(TA_STATE_ISPCTL);
pvr_csb_pack (cs_ptr, TA_STATE_ISPA, ispa) {
ispa.objtype = PVRX(TA_OBJTYPE_TRIANGLE);
ispa.passtype = read_bgnd ? PVRX(TA_PASSTYPE_TRANSLUCENT)
: PVRX(TA_PASSTYPE_OPAQUE);
ispa.dcmpmode = PVRX(TA_CMPMODE_ALWAYS);
ispa.objtype = ROGUE_TA_OBJTYPE_TRIANGLE;
ispa.passtype = read_bgnd ? ROGUE_TA_PASSTYPE_TRANSLUCENT
: ROGUE_TA_PASSTYPE_OPAQUE;
ispa.dcmpmode = ROGUE_TA_CMPMODE_ALWAYS;
ispa.dwritedisable = true;
}
cs_ptr += pvr_cmd_length(TA_STATE_ISPA);
@ -3343,14 +3343,14 @@ static void pvr_isp_prim_block_isp_state(const struct pvr_device_info *dev_info,
/* ISP vertex compression. */
pvr_csb_pack (cs_ptr, IPF_ISP_COMPRESSION_WORD_0, word0) {
word0.cf_isp_comp_fmt_x0 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_x1 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_x2 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_y0 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_y1 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_y2 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_z0 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_z1 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word0.cf_isp_comp_fmt_x0 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_x1 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_x2 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_y0 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_y1 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_y2 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_z0 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word0.cf_isp_comp_fmt_z1 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
}
cs_ptr += pvr_cmd_length(IPF_ISP_COMPRESSION_WORD_0);
@ -3359,8 +3359,8 @@ static void pvr_isp_prim_block_isp_state(const struct pvr_device_info *dev_info,
word1.vf_prim_id_pres = 0U;
word1.vf_vertex_clipped = 0U;
word1.vf_vertex_total = num_isp_vertices - 1U;
word1.cf_isp_comp_fmt_z3 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word1.cf_isp_comp_fmt_z2 = PVRX(IPF_COMPRESSION_FORMAT_RAW_BYTE);
word1.cf_isp_comp_fmt_z3 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
word1.cf_isp_comp_fmt_z2 = ROGUE_IPF_COMPRESSION_FORMAT_RAW_BYTE;
}
cs_ptr += pvr_cmd_length(IPF_ISP_COMPRESSION_WORD_1);
@ -3457,14 +3457,14 @@ pvr_int32_to_isp_xy_vtx(const struct pvr_device_info *dev_info,
uint32_t *word_out)
{
if (PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format)) {
const uint32_t max_fractional = PVRX(IPF_ISP_VERTEX_XY_SIPF_FRAC_MAX_VAL);
const uint32_t max_integer = PVRX(IPF_ISP_VERTEX_XY_SIPF_INTEGER_MAX_VAL);
const uint32_t max_fractional = ROGUE_IPF_ISP_VERTEX_XY_SIPF_FRAC_MAX_VAL;
const uint32_t max_integer = ROGUE_IPF_ISP_VERTEX_XY_SIPF_INTEGER_MAX_VAL;
uint32_t fractional;
uint32_t integer;
if (bias)
val += PVRX(IPF_ISP_VERTEX_XY_BIAS_VALUE_SIPF);
val += ROGUE_IPF_ISP_VERTEX_XY_BIAS_VALUE_SIPF;
if (val < 0 || val > max_integer + 1) {
mesa_loge("ISP vertex xy value out of range.");
@ -3492,7 +3492,7 @@ pvr_int32_to_isp_xy_vtx(const struct pvr_device_info *dev_info,
return VK_SUCCESS;
}
val += PVRX(IPF_ISP_VERTEX_XY_BIAS_VALUE);
val += ROGUE_IPF_ISP_VERTEX_XY_BIAS_VALUE;
if (((uint32_t)val & 0x7fff8000U) != 0U)
return vk_error(NULL, VK_ERROR_UNKNOWN);
@ -3594,7 +3594,7 @@ pvr_isp_prim_block_isp_vertices(const struct pvr_device_info *dev_info,
cs_ptr++;
pvr_csb_pack (cs_ptr, IPF_ISP_VERTEX_WORD_1, word1) {
word1.y0 = top >> PVRX(IPF_ISP_VERTEX_WORD_1_Y0_SHIFT);
word1.y0 = top >> ROGUE_IPF_ISP_VERTEX_WORD_1_Y0_SHIFT;
}
cs_ptr++;
@ -3605,7 +3605,7 @@ pvr_isp_prim_block_isp_vertices(const struct pvr_device_info *dev_info,
cs_ptr++;
pvr_csb_pack (cs_ptr, IPF_ISP_VERTEX_WORD_3, word3) {
word3.x1 = right >> PVRX(IPF_ISP_VERTEX_WORD_3_X1_SHIFT);
word3.x1 = right >> ROGUE_IPF_ISP_VERTEX_WORD_3_X1_SHIFT;
word3.y1 = top;
}
cs_ptr++;
@ -3623,7 +3623,7 @@ pvr_isp_prim_block_isp_vertices(const struct pvr_device_info *dev_info,
cs_ptr++;
pvr_csb_pack (cs_ptr, IPF_ISP_VERTEX_WORD_1, word1) {
word1.y0 = bottom >> PVRX(IPF_ISP_VERTEX_WORD_1_Y0_SHIFT);
word1.y0 = bottom >> ROGUE_IPF_ISP_VERTEX_WORD_1_Y0_SHIFT;
}
cs_ptr++;
@ -3634,7 +3634,7 @@ pvr_isp_prim_block_isp_vertices(const struct pvr_device_info *dev_info,
cs_ptr++;
pvr_csb_pack (cs_ptr, IPF_ISP_VERTEX_WORD_3, word3) {
word3.x1 = right >> PVRX(IPF_ISP_VERTEX_WORD_3_X1_SHIFT);
word3.x1 = right >> ROGUE_IPF_ISP_VERTEX_WORD_3_X1_SHIFT;
word3.y1 = bottom;
}
cs_ptr++;
@ -3858,7 +3858,7 @@ pvr_isp_primitive_block(const struct pvr_device_info *dev_info,
static inline uint32_t
pvr_transfer_prim_blocks_per_alloc(const struct pvr_device_info *dev_info)
{
uint32_t ret = PVR_DW_TO_BYTES(PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS));
uint32_t ret = PVR_DW_TO_BYTES(ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS);
if (PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format))
return ret / sizeof(uint64_t) / 2U;
@ -3907,7 +3907,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
{
const uint32_t max_mappings_per_pb = pvr_transfer_max_quads_per_pb(dev_info);
bool fill_blit = (transfer_cmd->flags & PVR_TRANSFER_CMD_FLAGS_FILL) != 0U;
uint32_t free_ctrl_stream_words = PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS);
uint32_t free_ctrl_stream_words = ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS;
struct pvr_transfer_3d_state *const state = &prep_data->state;
struct pvr_winsys_transfer_regs *const regs = &state->regs;
struct pvr_transfer_pass *pass = NULL;
@ -3985,7 +3985,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
num_region_arrays =
(num_prim_blks + (pvr_transfer_prim_blocks_per_alloc(dev_info) - 1U)) /
pvr_transfer_prim_blocks_per_alloc(dev_info);
region_arrays_size = PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS) *
region_arrays_size = ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS *
sizeof(uint32_t) * num_region_arrays;
total_stream_size = region_arrays_size + prim_blk_size;
@ -4228,7 +4228,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
num_region_arrays++;
next_region_array_vaddr.addr +=
num_region_arrays *
PVR_DW_TO_BYTES(PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS));
PVR_DW_TO_BYTES(ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS);
if (PVR_HAS_FEATURE(dev_info,
simple_internal_parameter_format_v2)) {
@ -4238,7 +4238,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
IPF_CONTROL_STREAM_LINK_SIPF2,
control_stream) {
control_stream.cs_ctrl_type =
PVRX(IPF_CS_CTRL_TYPE_SIPF2_LINK);
ROGUE_IPF_CS_CTRL_TYPE_SIPF2_LINK;
control_stream.cs_link.addr = next_region_array_vaddr.addr;
}
@ -4249,15 +4249,15 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
pvr_cmd_length(IPF_CONTROL_STREAM_LINK_SIPF2)));
} else {
pvr_csb_pack (cs_ptr, IPF_CONTROL_STREAM, control_stream) {
control_stream.cs_type = PVRX(IPF_CS_TYPE_LINK);
control_stream.cs_type = ROGUE_IPF_CS_TYPE_LINK;
control_stream.cs_link.addr = next_region_array_vaddr.addr;
}
}
cs_ptr =
(uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_cs_bo) +
num_region_arrays * PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS);
free_ctrl_stream_words = PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS);
num_region_arrays * ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS;
free_ctrl_stream_words = ROGUE_IPF_CONTROL_STREAM_SIZE_DWORDS;
was_linked = PVR_HAS_FEATURE(dev_info, ipf_creq_pf);
}
@ -4353,11 +4353,11 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
free_ctrl_stream_words -= 2;
} else {
pvr_csb_pack (cs_ptr, IPF_PRIMITIVE_FORMAT, word) {
word.cs_type = PVRX(IPF_CS_TYPE_PRIM);
word.cs_type = ROGUE_IPF_CS_TYPE_PRIM;
word.cs_isp_state_read = true;
word.cs_isp_state_size = 2U;
word.cs_prim_total = 2U * num_mappings - 1U;
word.cs_mask_fmt = PVRX(IPF_CS_MASK_FMT_FULL);
word.cs_mask_fmt = ROGUE_IPF_CS_MASK_FMT_FULL;
word.cs_prim_base_pres = true;
}
cs_ptr += pvr_cmd_length(IPF_PRIMITIVE_FORMAT);
@ -4405,7 +4405,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
cs_ptr = (uint32_t *)cs_byte_ptr;
} else {
pvr_csb_pack (cs_ptr, IPF_CONTROL_STREAM, word) {
word.cs_type = PVRX(IPF_CS_TYPE_TERM);
word.cs_type = ROGUE_IPF_CS_TYPE_TERM;
}
cs_ptr += pvr_cmd_length(IPF_CONTROL_STREAM);
}
@ -4417,7 +4417,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
}
pvr_csb_pack (&regs->isp_render, CR_ISP_RENDER, reg) {
reg.mode_type = PVRX(CR_ISP_RENDER_MODE_TYPE_FAST_2D);
reg.mode_type = ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_2D;
}
if (PVR_HAS_FEATURE(dev_info, simple_internal_parameter_format_v2) &&
@ -4575,7 +4575,7 @@ static inline bool pvr_is_pbe_stride_aligned(const uint32_t stride)
if (stride == 1U)
return true;
return ((stride & (PVRX(PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE) - 1U)) ==
return ((stride & (ROGUE_PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE - 1U)) ==
0x0U);
}
@ -5597,7 +5597,7 @@ static bool pvr_validate_source_addr(pvr_dev_addr_t addr)
{
if (!pvr_dev_addr_is_aligned(
addr,
PVRX(TEXSTATE_STRIDE_IMAGE_WORD1_TEXADDR_ALIGNMENT))) {
ROGUE_TEXSTATE_STRIDE_IMAGE_WORD1_TEXADDR_ALIGNMENT)) {
return false;
}
@ -5646,7 +5646,7 @@ static bool pvr_3d_validate_addr(struct pvr_transfer_cmd *transfer_cmd)
if (!pvr_supports_texel_unwind(transfer_cmd)) {
return pvr_dev_addr_is_aligned(
transfer_cmd->dst.dev_addr,
PVRX(PBESTATE_STATE_WORD0_ADDRESS_LOW_ALIGNMENT));
ROGUE_PBESTATE_STATE_WORD0_ADDRESS_LOW_ALIGNMENT);
}
return true;

4
src/imagination/vulkan/pvr_limits.h
View file

@ -40,9 +40,9 @@
#define PVR_MAX_PUSH_CONSTANTS_SIZE 256U
#define PVR_MAX_TEXTURE_EXTENT_Z \
(PVRX(TEXSTATE_IMAGE_WORD1_DEPTH_MAX_SIZE) + 1U)
(ROGUE_TEXSTATE_IMAGE_WORD1_DEPTH_MAX_SIZE + 1U)
#define PVR_MAX_ARRAY_LAYERS (PVRX(TEXSTATE_IMAGE_WORD1_DEPTH_MAX_SIZE) + 1U)
#define PVR_MAX_ARRAY_LAYERS (ROGUE_TEXSTATE_IMAGE_WORD1_DEPTH_MAX_SIZE + 1U)
#define PVR_MAX_DESCRIPTOR_SETS 4U
#define PVR_MAX_DESCRIPTOR_SET_UNIFORM_DYNAMIC_BUFFERS 8U

2
src/imagination/vulkan/pvr_pass.c
View file

@ -129,7 +129,7 @@ pvr_init_subpass_isp_userpass(struct pvr_renderpass_hwsetup *hw_setup,
for (uint32_t j = 0; j < hw_render->subpass_count; j++) {
subpasses[subpass_idx].isp_userpass =
(j + initial_isp_userpass) & PVRX(CR_ISP_CTL_UPASS_START_SIZE_MAX);
(j + initial_isp_userpass) & ROGUE_CR_ISP_CTL_UPASS_START_SIZE_MAX;
subpass_idx++;
}
}

10
src/imagination/vulkan/pvr_pipeline.c
View file

@ -150,8 +150,8 @@ VkResult pvr_pds_fragment_program_create_and_upload(
bool has_phase_rate_change,
struct pvr_pds_upload *const pds_upload_out)
{
const enum PVRX(PDSINST_DOUTU_SAMPLE_RATE)
sample_rate = pvr_pdsinst_doutu_sample_rate(msaa_mode);
const enum ROGUE_PDSINST_DOUTU_SAMPLE_RATE sample_rate =
pvr_pdsinst_doutu_sample_rate(msaa_mode);
struct pvr_pds_kickusc_program program = { 0 };
uint32_t staging_buffer_size;
uint32_t *staging_buffer;
@ -444,7 +444,7 @@ static VkResult pvr_pds_vertex_attrib_programs_create_and_upload(
pvr_pds_setup_doutu(&input.usc_task_control,
0,
usc_temp_count,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
/* Note: programs_out_ptr is a pointer to an array so this is fine. See the
@ -715,7 +715,7 @@ static void pvr_pds_compute_program_setup(
pvr_pds_setup_doutu(&program->usc_task_control,
usc_shader_dev_addr.addr,
usc_temps,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_compute_shader(program, NULL, PDS_GENERATE_SIZES, dev_info);
@ -1302,7 +1302,7 @@ pvr_fragment_state_init(struct pvr_graphics_pipeline *gfx_pipeline,
fragment_state->stage_state.has_side_effects = false;
fragment_state->stage_state.empty_program = false;
fragment_state->pass_type = PVRX(TA_PASSTYPE_OPAQUE);
fragment_state->pass_type = ROGUE_TA_PASSTYPE_OPAQUE;
fragment_state->entry_offset = 0;
/* We can't initialize it yet since we still need to generate the PDS

8
src/imagination/vulkan/pvr_private.h
View file

@ -402,7 +402,7 @@ struct pvr_transfer_cmd_source {
/* In the case of a simple 1:1 copy, this setting does not affect the output
* but will affect performance. Use clamp to edge when possible.
*/
/* This is of type enum PVRX(TEXSTATE_ADDRMODE). */
/* This is of type enum ROGUE_TEXSTATE_ADDRMODE. */
int addr_mode;
/* Source filtering method. */
@ -610,7 +610,7 @@ struct pvr_ppp_state {
struct {
/* TODO: Can we get rid of the "control" field? */
struct PVRX(TA_STATE_ISPCTL) control_struct;
struct ROGUE_TA_STATE_ISPCTL control_struct;
uint32_t control;
uint32_t front_a;
@ -697,7 +697,7 @@ struct pvr_cmd_buffer_state {
struct pvr_ppp_state ppp_state;
struct PVRX(TA_STATE_HEADER) emit_header;
struct ROGUE_TA_STATE_HEADER emit_header;
struct pvr_vertex_binding vertex_bindings[PVR_MAX_VERTEX_INPUT_BINDINGS];
@ -915,7 +915,7 @@ struct pvr_fragment_shader_state {
struct pvr_pipeline_stage_state stage_state;
/* FIXME: Move this into stage_state? */
struct pvr_stage_allocation_descriptor_state descriptor_state;
enum PVRX(TA_PASSTYPE) pass_type;
enum ROGUE_TA_PASSTYPE pass_type;
struct pvr_pds_upload pds_coeff_program;
struct pvr_pds_upload pds_fragment_program;

4
src/imagination/vulkan/pvr_query.c
View file

@ -69,7 +69,7 @@ VkResult pvr_CreateQueryPool(VkDevice _device,
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
pool->result_stride =
ALIGN_POT(query_size, PVRX(CR_ISP_OCLQRY_BASE_ADDR_ALIGNMENT));
ALIGN_POT(query_size, ROGUE_CR_ISP_OCLQRY_BASE_ADDR_ALIGNMENT);
pool->query_count = pCreateInfo->queryCount;
@ -80,7 +80,7 @@ VkResult pvr_CreateQueryPool(VkDevice _device,
result = pvr_bo_suballoc(&device->suballoc_vis_test,
alloc_size,
PVRX(CR_ISP_OCLQRY_BASE_ADDR_ALIGNMENT),
ROGUE_CR_ISP_OCLQRY_BASE_ADDR_ALIGNMENT,
false,
&pool->result_buffer);
if (result != VK_SUCCESS)

14
src/imagination/vulkan/pvr_query_compute.c
View file

@ -161,7 +161,7 @@ static VkResult pvr_create_compute_query_program(
pvr_pds_setup_doutu(&pds_primary_prog.usc_task_control,
query_prog->usc_bo->dev_addr.addr,
shader_factory_info->temps_required,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
result =
@ -499,13 +499,13 @@ VkResult pvr_add_query_program(struct pvr_cmd_buffer *cmd_buffer,
VkResult result;
pvr_csb_pack (&sampler_state[0U], TEXSTATE_SAMPLER, reg) {
reg.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.addrmode_w = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
reg.minfilter = PVRX(TEXSTATE_FILTER_POINT);
reg.magfilter = PVRX(TEXSTATE_FILTER_POINT);
reg.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
reg.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
reg.addrmode_w = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
reg.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
reg.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
reg.non_normalized_coords = true;
reg.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
reg.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
}
/* clang-format off */

50
src/imagination/vulkan/pvr_spm.c
View file

@ -110,7 +110,7 @@ pvr_spm_scratch_buffer_calc_required_size(const struct pvr_render_pass *pass,
(uint64_t)pass->max_sample_count * nr_output_regs * nr_tile_buffers;
buffer_size = ALIGN_POT((uint64_t)framebuffer_width,
PVRX(CR_PBE_WORD0_MRT0_LINESTRIDE_ALIGNMENT));
ROGUE_CR_PBE_WORD0_MRT0_LINESTRIDE_ALIGNMENT);
buffer_size *=
(uint64_t)framebuffer_height * PVR_DW_TO_BYTES(dwords_per_pixel);
@ -358,16 +358,16 @@ VkResult pvr_device_init_spm_load_state(struct pvr_device *device)
const pvr_dev_addr_t usc_program_dev_addr =
PVR_DEV_ADDR_OFFSET(usc_bo->dev_addr, usc_aligned_offsets[i]);
struct pvr_pds_kickusc_program pds_kick_program = { 0 };
enum PVRX(PDSINST_DOUTU_SAMPLE_RATE) sample_rate;
enum ROGUE_PDSINST_DOUTU_SAMPLE_RATE sample_rate;
pvr_pds_generate_pixel_shader_sa_code_segment(
&pds_texture_program,
(uint32_t *)(mem_ptr + pds_texture_aligned_offsets[i]));
if (spm_load_collection[i].info->msaa_sample_count > 1)
sample_rate = PVRX(PDSINST_DOUTU_SAMPLE_RATE_FULL);
sample_rate = ROGUE_PDSINST_DOUTU_SAMPLE_RATE_FULL;
else
sample_rate = PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE);
sample_rate = ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE;
pvr_pds_setup_doutu(&pds_kick_program.usc_task_control,
usc_program_dev_addr.addr,
@ -405,18 +405,18 @@ void pvr_device_finish_spm_load_state(struct pvr_device *device)
pvr_bo_suballoc_free(device->spm_load_state.usc_programs);
}
static inline enum PVRX(PBESTATE_PACKMODE)
pvr_spm_get_pbe_packmode(uint32_t dword_count)
static inline enum ROGUE_PBESTATE_PACKMODE
pvr_spm_get_pbe_packmode(uint32_t dword_count)
{
switch (dword_count) {
case 1:
return PVRX(PBESTATE_PACKMODE_U32);
return ROGUE_PBESTATE_PACKMODE_U32;
case 2:
return PVRX(PBESTATE_PACKMODE_U32U32);
return ROGUE_PBESTATE_PACKMODE_U32U32;
case 3:
return PVRX(PBESTATE_PACKMODE_U32U32U32);
return ROGUE_PBESTATE_PACKMODE_U32U32U32;
case 4:
return PVRX(PBESTATE_PACKMODE_U32U32U32U32);
return ROGUE_PBESTATE_PACKMODE_U32U32U32U32;
default:
unreachable("Unsupported dword_count");
}
@ -444,7 +444,7 @@ static uint64_t pvr_spm_setup_pbe_state(
{
const uint32_t stride =
ALIGN_POT(framebuffer_size->width,
PVRX(PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE));
ROGUE_PBESTATE_REG_WORD0_LINESTRIDE_UNIT_SIZE);
const struct pvr_pbe_surf_params surface_params = {
.swizzle = {
@ -454,7 +454,7 @@ static uint64_t pvr_spm_setup_pbe_state(
[3] = PIPE_SWIZZLE_W,
},
.pbe_packmode = pvr_spm_get_pbe_packmode(dword_count),
.source_format = PVRX(PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL),
.source_format = ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL,
.addr = scratch_buffer_addr,
.mem_layout = PVR_MEMLAYOUT_LINEAR,
.stride = stride,
@ -576,7 +576,7 @@ static VkResult pvr_pds_pixel_event_program_create_and_upload(
pvr_pds_setup_doutu(&program.task_control,
usc_eot_program->dev_addr.addr,
usc_temp_count,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
staging_buffer =
@ -815,7 +815,7 @@ static VkResult pvr_spm_setup_texture_state_words(
};
const uint64_t aligned_fb_width =
ALIGN_POT(framebuffer_size.width,
PVRX(CR_PBE_WORD0_MRT0_LINESTRIDE_ALIGNMENT));
ROGUE_CR_PBE_WORD0_MRT0_LINESTRIDE_ALIGNMENT);
const uint64_t fb_area = aligned_fb_width * framebuffer_size.height;
const uint8_t *format_swizzle;
VkResult result;
@ -855,7 +855,7 @@ static VkResult pvr_pds_bgnd_program_create_and_upload(
pvr_csb_pack (&texture_program.texture_dma_control[0],
PDSINST_DOUT_FIELDS_DOUTD_SRC1,
doutd_src1) {
doutd_src1.dest = PVRX(PDSINST_DOUTD_DEST_COMMON_STORE);
doutd_src1.dest = ROGUE_PDSINST_DOUTD_DEST_COMMON_STORE;
doutd_src1.bsize = const_shared_regs;
}
@ -980,13 +980,13 @@ pvr_spm_init_bgobj_state(struct pvr_device *device,
pvr_csb_pack (&descriptor->data.sampler_word, TEXSTATE_SAMPLER, sampler) {
sampler.non_normalized_coords = true;
sampler.addrmode_v = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.addrmode_u = PVRX(TEXSTATE_ADDRMODE_CLAMP_TO_EDGE);
sampler.minfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.magfilter = PVRX(TEXSTATE_FILTER_POINT);
sampler.maxlod = PVRX(TEXSTATE_CLAMP_MIN);
sampler.minlod = PVRX(TEXSTATE_CLAMP_MIN);
sampler.dadjust = PVRX(TEXSTATE_DADJUST_ZERO_UINT);
sampler.addrmode_v = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.addrmode_u = ROGUE_TEXSTATE_ADDRMODE_CLAMP_TO_EDGE;
sampler.minfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.magfilter = ROGUE_TEXSTATE_FILTER_POINT;
sampler.maxlod = ROGUE_TEXSTATE_CLAMP_MIN;
sampler.minlod = ROGUE_TEXSTATE_CLAMP_MIN;
sampler.dadjust = ROGUE_TEXSTATE_DADJUST_ZERO_UINT;
}
/* Even if we might have 8 output regs we can only pack and write 4 dwords
@ -1062,13 +1062,13 @@ pvr_spm_init_bgobj_state(struct pvr_device *device,
/* clang-format on */
value.usc_sharedsize =
DIV_ROUND_UP(info->const_shared_regs,
PVRX(CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_USC_SHAREDSIZE_UNIT_SIZE);
value.pds_texturestatesize = DIV_ROUND_UP(
pds_texture_data_upload.data_size,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEXTURESTATESIZE_UNIT_SIZE);
value.pds_tempsize =
DIV_ROUND_UP(load_program_state->pds_texture_program_temps_count,
PVRX(CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE));
ROGUE_CR_PDS_BGRND3_SIZEINFO_PDS_TEMPSIZE_UNIT_SIZE);
}
return VK_SUCCESS;

20
src/imagination/vulkan/pvr_tex_state.c
View file

@ -90,7 +90,7 @@ pvr_pack_tex_state(struct pvr_device *device,
switch (iview_type) {
case VK_IMAGE_VIEW_TYPE_2D:
case VK_IMAGE_VIEW_TYPE_2D_ARRAY:
word0.textype = PVRX(TEXSTATE_TEXTYPE_STRIDE);
word0.textype = ROGUE_TEXSTATE_TEXTYPE_STRIDE;
break;
default:
@ -100,17 +100,17 @@ pvr_pack_tex_state(struct pvr_device *device,
switch (iview_type) {
case VK_IMAGE_VIEW_TYPE_1D:
case VK_IMAGE_VIEW_TYPE_1D_ARRAY:
word0.textype = PVRX(TEXSTATE_TEXTYPE_1D);
word0.textype = ROGUE_TEXSTATE_TEXTYPE_1D;
break;
case VK_IMAGE_VIEW_TYPE_2D:
case VK_IMAGE_VIEW_TYPE_2D_ARRAY:
word0.textype = PVRX(TEXSTATE_TEXTYPE_2D);
word0.textype = ROGUE_TEXSTATE_TEXTYPE_2D;
break;
case VK_IMAGE_VIEW_TYPE_CUBE:
case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY:
word0.textype = PVRX(TEXSTATE_TEXTYPE_CUBE);
word0.textype = ROGUE_TEXSTATE_TEXTYPE_CUBE;
break;
default:
@ -119,7 +119,7 @@ pvr_pack_tex_state(struct pvr_device *device,
} else if (mem_layout == PVR_MEMLAYOUT_3DTWIDDLED) {
switch (iview_type) {
case VK_IMAGE_VIEW_TYPE_3D:
word0.textype = PVRX(TEXSTATE_TEXTYPE_3D);
word0.textype = ROGUE_TEXSTATE_TEXTYPE_3D;
break;
default:
@ -154,10 +154,10 @@ pvr_pack_tex_state(struct pvr_device *device,
* Channel.
*/
if (vk_format_has_alpha(info->format)) {
word0.twocomp_gamma = PVRX(TEXSTATE_TWOCOMP_GAMMA_R);
word0.twocomp_gamma = ROGUE_TEXSTATE_TWOCOMP_GAMMA_R;
} else {
/* Otherwise Enable Gamma for both the Channels. */
word0.twocomp_gamma = PVRX(TEXSTATE_TWOCOMP_GAMMA_RG);
word0.twocomp_gamma = ROGUE_TEXSTATE_TWOCOMP_GAMMA_RG;
/* If Channel 0 happens to be the Alpha Channel, the
* ALPHA_MSB bit would not be set thereby disabling Gamma
@ -165,7 +165,7 @@ pvr_pack_tex_state(struct pvr_device *device,
*/
}
} else {
word0.gamma = PVRX(TEXSTATE_GAMMA_ON);
word0.gamma = ROGUE_TEXSTATE_GAMMA_ON;
}
}
@ -200,7 +200,7 @@ pvr_pack_tex_state(struct pvr_device *device,
if (PVR_HAS_FEATURE(dev_info, tpu_image_state_v2) &&
vk_format_is_compressed(info->format))
word1.tpu_image_state_v2_compression_mode =
PVRX(TEXSTATE_COMPRESSION_MODE_TPU);
ROGUE_TEXSTATE_COMPRESSION_MODE_TPU;
}
} else {
pvr_csb_pack (&state[1], TEXSTATE_IMAGE_WORD1, word1) {
@ -242,7 +242,7 @@ pvr_pack_tex_state(struct pvr_device *device,
if (PVR_HAS_FEATURE(dev_info, tpu_image_state_v2) &&
vk_format_is_compressed(info->format))
word1.tpu_image_state_v2_compression_mode =
PVRX(TEXSTATE_COMPRESSION_MODE_TPU);
ROGUE_TEXSTATE_COMPRESSION_MODE_TPU;
}
}

4
src/imagination/vulkan/pvr_transfer_frag_store.c
View file

@ -255,8 +255,8 @@ static VkResult pvr_transfer_frag_store_entry_data_create(
dev_addr.addr,
num_usc_temps,
shader_props->full_rate
? PVRX(PDSINST_DOUTU_SAMPLE_RATE_FULL)
: PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
? ROGUE_PDSINST_DOUTU_SAMPLE_RATE_FULL
: ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_kick_usc(&kick_usc_pds_prog, NULL, 0U, false, PDS_GENERATE_SIZES);

2
src/imagination/vulkan/winsys/pvr_winsys_helper.c
View file

@ -290,7 +290,7 @@ static void pvr_setup_static_vdm_sync(uint8_t *const pds_ptr,
pvr_pds_setup_doutu(&ppp_state_update_program.usc_task_control,
usc_sync_offset_in_bytes,
0,
PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE),
ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE,
false);
pvr_pds_kick_usc(&ppp_state_update_program,

2
src/imagination/vulkan/winsys/pvrsrvkm/pvr_srv_job_compute.c
View file

@ -195,7 +195,7 @@ static void pvr_srv_compute_cmd_ext_stream_load(
(const uint32_t *)((uint8_t *)stream + ext_stream_offset);
struct rogue_fwif_cdm_regs *const regs = &cmd->regs;
struct PVRX(KMD_STREAM_EXTHDR_COMPUTE0) header0;
struct ROGUE_KMD_STREAM_EXTHDR_COMPUTE0 header0;
header0 = pvr_csb_unpack(ext_stream_ptr, KMD_STREAM_EXTHDR_COMPUTE0);
ext_stream_ptr += pvr_cmd_length(KMD_STREAM_EXTHDR_COMPUTE0);

4
src/imagination/vulkan/winsys/pvrsrvkm/pvr_srv_job_render.c
View file

@ -683,7 +683,7 @@ static void pvr_srv_geometry_cmd_ext_stream_load(
(const uint32_t *)((uint8_t *)stream + ext_stream_offset);
struct rogue_fwif_ta_regs *const regs = &cmd->regs;
struct PVRX(KMD_STREAM_EXTHDR_GEOM0) header0;
struct ROGUE_KMD_STREAM_EXTHDR_GEOM0 header0;
header0 = pvr_csb_unpack(ext_stream_ptr, KMD_STREAM_EXTHDR_GEOM0);
ext_stream_ptr += pvr_cmd_length(KMD_STREAM_EXTHDR_GEOM0);
@ -866,7 +866,7 @@ static void pvr_srv_fragment_cmd_ext_stream_load(
(const uint32_t *)((uint8_t *)stream + ext_stream_offset);
struct rogue_fwif_3d_regs *const regs = &cmd->regs;
struct PVRX(KMD_STREAM_EXTHDR_FRAG0) header0;
struct ROGUE_KMD_STREAM_EXTHDR_FRAG0 header0;
header0 = pvr_csb_unpack(ext_stream_ptr, KMD_STREAM_EXTHDR_FRAG0);
ext_stream_ptr += pvr_cmd_length(KMD_STREAM_EXTHDR_FRAG0);