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intel/brw: Pull lower_pack out of fs_visitor

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26887>
This commit is contained in:
Caio Oliveira 2024-01-03 15:37:32 -08:00 • committed by Marge Bot
parent f6b82b0270
commit 14954cbd58
3 changed files with 7 additions and 7 deletions
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2
src/intel/compiler/brw_fs.cpp
View file

@ -5696,7 +5696,7 @@ fs_visitor::optimize()
progress = false;
pass_num = 0;
if (OPT(lower_pack)) {
if (OPT(brw_fs_lower_pack, *this)) {
OPT(brw_fs_opt_register_coalesce, *this);
OPT(brw_fs_opt_dead_code_eliminate, *this);
}

2
src/intel/compiler/brw_fs.h
View file

@ -274,7 +274,6 @@ public:
void limit_dispatch_width(unsigned n, const char *msg);
bool lower_uniform_pull_constant_loads();
bool lower_load_payload();
bool lower_pack();
bool lower_regioning();
bool lower_logical_sends();
bool lower_integer_multiplication();
@ -606,6 +605,7 @@ bool brw_lower_dpas(fs_visitor &v);
void nir_to_brw(fs_visitor *s);
bool brw_fs_lower_constant_loads(fs_visitor &s);
bool brw_fs_lower_pack(fs_visitor &s);
bool brw_fs_opt_algebraic(fs_visitor &s);
bool brw_fs_opt_bank_conflicts(fs_visitor &s);

10
src/intel/compiler/brw_fs_lower_pack.cpp
View file

@ -29,11 +29,11 @@
using namespace brw;
bool
fs_visitor::lower_pack()
brw_fs_lower_pack(fs_visitor &s)
{
bool progress = false;
foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) {
if (inst->opcode != FS_OPCODE_PACK &&
inst->opcode != FS_OPCODE_PACK_HALF_2x16_SPLIT)
continue;
@ -42,7 +42,7 @@ fs_visitor::lower_pack()
assert(inst->saturate == false);
fs_reg dst = inst->dst;
const fs_builder ibld(this, block, inst);
const fs_builder ibld(&s, block, inst);
/* The lowering generates 2 instructions for what was previously 1. This
* can trick the IR to believe we're doing partial writes, but the
* register is actually fully written. Mark it as undef to help the IR
@ -64,7 +64,7 @@ fs_visitor::lower_pack()
const uint32_t half = _mesa_float_to_half(inst->src[i].f);
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, i),
brw_imm_uw(half));
} else if (i == 1 && devinfo->ver < 9) {
} else if (i == 1 && s.devinfo->ver < 9) {
/* Pre-Skylake requires DWord aligned destinations */
fs_reg tmp = ibld.vgrf(BRW_REGISTER_TYPE_UD);
ibld.F32TO16(subscript(tmp, BRW_REGISTER_TYPE_HF, 0),
@ -86,7 +86,7 @@ fs_visitor::lower_pack()
}
if (progress)
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
return progress;
}