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r600/sfn: Add support for atomic instructions
v2: fix compilation with gcc-6 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
This commit is contained in:
Gert Wollny
Marge Bot
parent
90a7d2e08f
commit
148f0ad4f9
6 changed files with 228 additions and 0 deletions
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@ -101,6 +101,8 @@ CXX_SOURCES = \
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sfn/sfn_emitaluinstruction.h \
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sfn/sfn_emitinstruction.cpp \
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sfn/sfn_emitinstruction.h \
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sfn/sfn_emitssboinstruction.cpp \
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sfn/sfn_emitssboinstruction.h \
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sfn/sfn_emittexinstruction.cpp \
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sfn/sfn_emittexinstruction.h \
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sfn/sfn_emitinstruction.h \
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@ -118,6 +118,8 @@ files_r600 = files(
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'sfn/sfn_emitaluinstruction.h',
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'sfn/sfn_emitinstruction.cpp',
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'sfn/sfn_emitinstruction.h',
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'sfn/sfn_emitssboinstruction.cpp',
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'sfn/sfn_emitssboinstruction.h',
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'sfn/sfn_emittexinstruction.cpp',
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'sfn/sfn_emittexinstruction.h',
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'sfn/sfn_emitinstruction.h',
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177
src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp
Normal file
177
src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp
Normal file
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@ -0,0 +1,177 @@
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#include "sfn_emitssboinstruction.h"
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#include "sfn_instruction_fetch.h"
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#include "sfn_instruction_gds.h"
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#include "sfn_instruction_misc.h"
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#include "../r600_pipe.h"
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namespace r600 {
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bool EmitSSBOInstruction::do_emit(nir_instr* instr)
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{
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const nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_atomic_counter_add:
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case nir_intrinsic_atomic_counter_and:
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case nir_intrinsic_atomic_counter_exchange:
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case nir_intrinsic_atomic_counter_max:
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case nir_intrinsic_atomic_counter_min:
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case nir_intrinsic_atomic_counter_or:
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case nir_intrinsic_atomic_counter_xor:
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case nir_intrinsic_atomic_counter_comp_swap:
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return emit_atomic(intr);
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case nir_intrinsic_atomic_counter_read:
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case nir_intrinsic_atomic_counter_post_dec:
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return emit_unary_atomic(intr);
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case nir_intrinsic_atomic_counter_inc:
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return emit_atomic_inc(intr);
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case nir_intrinsic_atomic_counter_pre_dec:
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return emit_atomic_pre_dec(intr);
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default:
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return false;
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}
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}
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bool EmitSSBOInstruction::emit_atomic(const nir_intrinsic_instr* instr)
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{
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ESDOp op = get_opcode(instr->intrinsic);
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if (DS_OP_INVALID == op)
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return false;
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GPRVector dest = make_dest(instr);
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int base = nir_intrinsic_base(instr);
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PValue uav_id = from_nir(instr->src[0], 0);
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PValue value = from_nir_with_fetch_constant(instr->src[1], 0);
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GDSInstr *ir = nullptr;
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if (instr->intrinsic == nir_intrinsic_atomic_counter_comp_swap) {
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PValue value2 = from_nir_with_fetch_constant(instr->src[1], 1);
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ir = new GDSInstr(op, dest, value, value2, uav_id, base);
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} else {
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ir = new GDSInstr(op, dest, value, uav_id, base);
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}
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emit_instruction(ir);
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return true;
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}
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bool EmitSSBOInstruction::emit_unary_atomic(const nir_intrinsic_instr* instr)
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{
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ESDOp op = get_opcode(instr->intrinsic);
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if (DS_OP_INVALID == op)
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return false;
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GPRVector dest = make_dest(instr);
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PValue uav_id = from_nir(instr->src[0], 0);
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auto ir = new GDSInstr(op, dest, uav_id, nir_intrinsic_base(instr));
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emit_instruction(ir);
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return true;
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}
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ESDOp EmitSSBOInstruction::get_opcode(const nir_intrinsic_op opcode)
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{
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switch (opcode) {
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case nir_intrinsic_atomic_counter_add:
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return DS_OP_ADD_RET;
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case nir_intrinsic_atomic_counter_and:
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return DS_OP_AND_RET;
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case nir_intrinsic_atomic_counter_exchange:
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return DS_OP_XCHG_RET;
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case nir_intrinsic_atomic_counter_inc:
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return DS_OP_INC_RET;
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case nir_intrinsic_atomic_counter_max:
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return DS_OP_MAX_UINT_RET;
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case nir_intrinsic_atomic_counter_min:
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return DS_OP_MIN_UINT_RET;
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case nir_intrinsic_atomic_counter_or:
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return DS_OP_OR_RET;
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case nir_intrinsic_atomic_counter_read:
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return DS_OP_READ_RET;
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case nir_intrinsic_atomic_counter_xor:
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return DS_OP_XOR_RET;
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case nir_intrinsic_atomic_counter_post_dec:
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return DS_OP_DEC_RET;
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case nir_intrinsic_atomic_counter_comp_swap:
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return DS_OP_CMP_XCHG_RET;
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case nir_intrinsic_atomic_counter_pre_dec:
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default:
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return DS_OP_INVALID;
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}
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}
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bool EmitSSBOInstruction::emit_atomic_add(const nir_intrinsic_instr* instr)
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{
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GPRVector dest = make_dest(instr);
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PValue value = from_nir_with_fetch_constant(instr->src[1], 0);
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PValue uav_id = from_nir(instr->src[0], 0);
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auto ir = new GDSInstr(DS_OP_ADD_RET, dest, value, uav_id,
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nir_intrinsic_base(instr));
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emit_instruction(ir);
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return true;
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}
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bool EmitSSBOInstruction::emit_atomic_inc(const nir_intrinsic_instr* instr)
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{
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GPRVector dest = make_dest(instr);
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PValue uav_id = from_nir(instr->src[0], 0);
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if (!m_atomic_limit) {
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int one_tmp = allocate_temp_register();
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m_atomic_limit = PValue(new GPRValue(one_tmp, 0));
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emit_instruction(new AluInstruction(op1_mov, m_atomic_limit,
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PValue(new LiteralValue(0xffffffff)),
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{alu_write, alu_last_instr}));
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}
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auto ir = new GDSInstr(DS_OP_INC_RET, dest, m_atomic_limit, uav_id,
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nir_intrinsic_base(instr));
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emit_instruction(ir);
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return true;
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}
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bool EmitSSBOInstruction::emit_atomic_pre_dec(const nir_intrinsic_instr *instr)
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{
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GPRVector dest = make_dest(instr);
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PValue uav_id = from_nir(instr->src[0], 0);
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int one_tmp = allocate_temp_register();
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PValue value(new GPRValue(one_tmp, 0));
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emit_instruction(new AluInstruction(op1_mov, value, Value::one_i,
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{alu_write, alu_last_instr}));
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auto ir = new GDSInstr(DS_OP_SUB_RET, dest, value, uav_id,
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nir_intrinsic_base(instr));
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emit_instruction(ir);
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ir = new GDSInstr(DS_OP_READ_RET, dest, uav_id, nir_intrinsic_base(instr));
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emit_instruction(ir);
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return true;
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}
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GPRVector EmitSSBOInstruction::make_dest(const nir_intrinsic_instr* ir)
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{
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GPRVector::Values v;
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int i;
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for (i = 0; i < 4; ++i)
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v[i] = from_nir(ir->dest, i);
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return GPRVector(v);
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}
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}
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29
src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h
Normal file
29
src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.h
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@ -0,0 +1,29 @@
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#ifndef SFN_EMITSSBOINSTRUCTION_H
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#define SFN_EMITSSBOINSTRUCTION_H
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#include "sfn_emitinstruction.h"
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namespace r600 {
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class EmitSSBOInstruction: public EmitInstruction {
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public:
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using EmitInstruction::EmitInstruction;
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private:
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bool do_emit(nir_instr *instr);
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bool emit_atomic(const nir_intrinsic_instr* instr);
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bool emit_unary_atomic(const nir_intrinsic_instr* instr);
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bool emit_atomic_add(const nir_intrinsic_instr* instr);
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bool emit_atomic_inc(const nir_intrinsic_instr* instr);
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bool emit_atomic_pre_dec(const nir_intrinsic_instr* instr);
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ESDOp get_opcode(nir_intrinsic_op opcode);
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GPRVector make_dest(const nir_intrinsic_instr* instr);
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PValue m_atomic_limit;
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};
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}
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#endif // SFN_EMITSSBOINSTRUCTION_H
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@ -62,6 +62,7 @@ ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype,
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m_sh_info(sh_info),
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m_tex_instr(*this),
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m_alu_instr(*this),
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m_ssbo_instr(*this),
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m_pending_else(nullptr),
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m_scratch_size(scratch_size),
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m_next_hwatomic_loc(0),
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@ -449,6 +450,21 @@ bool ShaderFromNirProcessor::emit_intrinsic_instruction(nir_intrinsic_instr* ins
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return emit_discard_if(instr);
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case nir_intrinsic_load_ubo_r600:
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return emit_load_ubo(instr);
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case nir_intrinsic_atomic_counter_add:
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case nir_intrinsic_atomic_counter_and:
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case nir_intrinsic_atomic_counter_exchange:
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case nir_intrinsic_atomic_counter_max:
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case nir_intrinsic_atomic_counter_min:
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case nir_intrinsic_atomic_counter_or:
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case nir_intrinsic_atomic_counter_xor:
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case nir_intrinsic_atomic_counter_comp_swap:
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case nir_intrinsic_atomic_counter_read:
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case nir_intrinsic_atomic_counter_post_dec:
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case nir_intrinsic_atomic_counter_inc:
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case nir_intrinsic_atomic_counter_pre_dec:
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m_sel.info.writes_memory = true;
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return m_ssbo_instr.emit(&instr->instr);
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break;
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case nir_intrinsic_copy_deref:
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case nir_intrinsic_load_constant:
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case nir_intrinsic_load_input:
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@ -40,6 +40,7 @@
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#include "sfn_instruction_cf.h"
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#include "sfn_emittexinstruction.h"
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#include "sfn_emitaluinstruction.h"
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#include "sfn_emitssboinstruction.h"
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#include <vector>
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#include <set>
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@ -174,6 +175,7 @@ private:
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EmitTexInstruction m_tex_instr;
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EmitAluInstruction m_alu_instr;
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EmitSSBOInstruction m_ssbo_instr;
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OutputRegisterMap m_output_register_map;
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IfElseInstruction *m_pending_else;
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