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radeonsi: fix the unaligned clear_buffer fallback with TC
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
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1 changed files with 7 additions and 1 deletions
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@ -420,7 +420,13 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
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assert(dst->target == PIPE_BUFFER);
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assert(size < 4);
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pipe_buffer_write(&sctx->b, dst, offset, size, clear_value);
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sctx->b.buffer_subdata(&sctx->b, dst,
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PIPE_MAP_WRITE |
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/* TC forbids drivers to invalidate buffers and infer unsychronized mappings,
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* so suppress those optimizations. */
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(sctx->tc ? TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED |
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TC_TRANSFER_MAP_NO_INVALIDATE : 0),
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offset, size, clear_value);
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}
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}
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