radeonsi: fix the unaligned clear_buffer fallback with TC

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
This commit is contained in:
Marek Olšák 2022-01-26 19:31:32 -05:00 committed by Marge Bot
parent 4e49a05e37
commit 1485f683e3

View file

@ -420,7 +420,13 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
assert(dst->target == PIPE_BUFFER);
assert(size < 4);
pipe_buffer_write(&sctx->b, dst, offset, size, clear_value);
sctx->b.buffer_subdata(&sctx->b, dst,
PIPE_MAP_WRITE |
/* TC forbids drivers to invalidate buffers and infer unsychronized mappings,
* so suppress those optimizations. */
(sctx->tc ? TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED |
TC_TRANSFER_MAP_NO_INVALIDATE : 0),
offset, size, clear_value);
}
}