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r600/uvd: cleanup disabling tiling on pre EG asics
Set transfer flag instead of fiddling with the tilling params directly. Signed-off-by: Christian König <christian.koenig@amd.com>
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7490eeb3d6
commit
13ddf9baf2
1 changed files with 6 additions and 5 deletions
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@ -76,6 +76,8 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
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template.height = align(tmpl->height / depth, VL_MACROBLOCK_HEIGHT);
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vl_vide_buffer_template(&templ, &template, resource_formats[0], depth, PIPE_USAGE_STATIC, 0);
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if (ctx->chip_class < EVERGREEN)
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templ.flags = R600_RESOURCE_FLAG_TRANSFER;
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resources[0] = (struct r600_texture *)
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pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[0])
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@ -83,6 +85,8 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
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if (resource_formats[1] != PIPE_FORMAT_NONE) {
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vl_vide_buffer_template(&templ, &template, resource_formats[1], depth, PIPE_USAGE_STATIC, 1);
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if (ctx->chip_class < EVERGREEN)
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templ.flags = R600_RESOURCE_FLAG_TRANSFER;
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resources[1] = (struct r600_texture *)
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pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[1])
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@ -91,6 +95,8 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
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if (resource_formats[2] != PIPE_FORMAT_NONE) {
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vl_vide_buffer_template(&templ, &template, resource_formats[2], depth, PIPE_USAGE_STATIC, 2);
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if (ctx->chip_class < EVERGREEN)
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templ.flags = R600_RESOURCE_FLAG_TRANSFER;
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resources[2] = (struct r600_texture *)
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pipe->screen->resource_create(pipe->screen, &templ);
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if (!resources[2])
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@ -103,11 +109,6 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
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pbs[i] = &resources[i]->resource.buf;
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surfaces[i] = &resources[i]->surface;
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if (ctx->chip_class < EVERGREEN) {
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resources[i]->array_mode[0] = V_038000_ARRAY_LINEAR_ALIGNED;
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resources[i]->surface.level[0].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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}
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ruvd_join_surfaces(ctx->ws, templ.bind, pbs, surfaces);
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