mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-08 08:30:10 +01:00
ac/gpu_info: fix querying the maximum number of IBs per ring
The kernel uses 32-bit and Mesa was using 8-bit...
Fixes: 96345ae2ed ("ac/gpu_info: query the maximum number of IBs per submit from the kernel")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25867>
This commit is contained in:
parent
3bf1b7deba
commit
13cac671fd
3 changed files with 5 additions and 3 deletions
|
|
@ -1544,7 +1544,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
|
|||
/* When the number of IBs can't be queried from the kernel, we choose a
|
||||
* rough estimate that should work well (as of kernel 6.3).
|
||||
*/
|
||||
memset(info->max_submitted_ibs, 50, AMD_NUM_IP_TYPES);
|
||||
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; ++i)
|
||||
info->max_submitted_ibs[i] = 50;
|
||||
|
||||
info->max_submitted_ibs[AMD_IP_GFX] = info->gfx_level >= GFX7 ? 192 : 144;
|
||||
info->max_submitted_ibs[AMD_IP_COMPUTE] = 124;
|
||||
info->max_submitted_ibs[AMD_IP_VCN_JPEG] = 16;
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ struct radeon_info {
|
|||
uint32_t drm_major; /* version */
|
||||
uint32_t drm_minor;
|
||||
uint32_t drm_patchlevel;
|
||||
uint8_t max_submitted_ibs[AMD_NUM_IP_TYPES];
|
||||
uint32_t max_submitted_ibs[AMD_NUM_IP_TYPES];
|
||||
bool is_amdgpu;
|
||||
bool has_userptr;
|
||||
bool has_syncobj;
|
||||
|
|
|
|||
|
|
@ -1017,7 +1017,7 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx, int queue_idx
|
|||
goto fail;
|
||||
|
||||
/* Configure the CS request. */
|
||||
const uint8_t *max_ib_per_ip = ws->info.max_submitted_ibs;
|
||||
const uint32_t *max_ib_per_ip = ws->info.max_submitted_ibs;
|
||||
struct radv_amdgpu_cs_request request = {
|
||||
.ip_type = last_cs->hw_ip,
|
||||
.ip_instance = 0,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue