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radv: move computing wave_size/ballot_bit_size to the shader info pass

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18278>
This commit is contained in:
Samuel Pitoiset 2022-08-26 11:59:06 +02:00 • committed by Marge Bot
parent 19308db39d
commit 13af51b2f3
2 changed files with 28 additions and 32 deletions
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32
src/amd/vulkan/radv_pipeline.c
View file

@ -3116,31 +3116,6 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
return key;
}
static uint8_t
radv_get_wave_size(struct radv_device *device, gl_shader_stage stage,
const struct radv_shader_info *info)
{
if (stage == MESA_SHADER_GEOMETRY && !info->is_ngg)
return 64;
else if (stage == MESA_SHADER_COMPUTE) {
return info->cs.subgroup_size;
} else if (stage == MESA_SHADER_FRAGMENT)
return device->physical_device->ps_wave_size;
else if (stage == MESA_SHADER_TASK)
return device->physical_device->cs_wave_size;
else
return device->physical_device->ge_wave_size;
}
static uint8_t
radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage,
const struct radv_shader_info *info)
{
if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size)
return info->cs.subgroup_size;
return 64;
}
static void
radv_determine_ngg_settings(struct radv_pipeline *pipeline,
const struct radv_pipeline_key *pipeline_key,
@ -3355,13 +3330,6 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
radv_nir_shader_info_link(device, pipeline_key, stages, last_vgt_api_stage);
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) {
if (stages[i].nir) {
stages[i].info.wave_size = radv_get_wave_size(device, i, &stages[i].info);
stages[i].info.ballot_bit_size = radv_get_ballot_bit_size(device, i, &stages[i].info);
}
}
if (stages[MESA_SHADER_TESS_CTRL].nir) {
for (gl_shader_stage s = MESA_SHADER_VERTEX; s <= MESA_SHADER_TESS_CTRL; ++s) {
stages[s].info.workgroup_size =

28
src/amd/vulkan/radv_shader_info.c
View file

@ -315,6 +315,31 @@ assign_outinfo_params(struct radv_vs_output_info *outinfo, uint64_t mask,
}
}
static uint8_t
radv_get_wave_size(struct radv_device *device, gl_shader_stage stage,
const struct radv_shader_info *info)
{
if (stage == MESA_SHADER_GEOMETRY && !info->is_ngg)
return 64;
else if (stage == MESA_SHADER_COMPUTE) {
return info->cs.subgroup_size;
} else if (stage == MESA_SHADER_FRAGMENT)
return device->physical_device->ps_wave_size;
else if (stage == MESA_SHADER_TASK)
return device->physical_device->cs_wave_size;
else
return device->physical_device->ge_wave_size;
}
static uint8_t
radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage,
const struct radv_shader_info *info)
{
if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size)
return info->cs.subgroup_size;
return 64;
}
static void
gather_info_input_decl_vs(const nir_shader *nir, unsigned location, const struct glsl_type *type,
const struct radv_pipeline_key *key, struct radv_shader_info *info)
@ -768,6 +793,9 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
default:
break;
}
info->wave_size = radv_get_wave_size(device, nir->info.stage, info);
info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info);
}
void