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intel/brw: Drop misguided sign extension attempts in extract_imm()

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This function never expands a type - it only narrows it.  As such, we
don't need to ever sign extend to fill additional new bits.  I think
this code was left over from earlier versions of my optimization pass
that was buggy and trying to handle cases it should not have.

Fixes: 580e1c592d ("intel/brw: Introduce a new SSA-based copy propagation pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30884>
(cherry picked from commit 51c85e0363)
This commit is contained in:
Kenneth Graunke 2024-08-12 13:13:48 -07:00 • committed by Eric Engestrom
parent b558fb259e
commit 139398f124
2 changed files with 2 additions and 11 deletions
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2
.pick_status.json
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@ -584,7 +584,7 @@
"description": "intel/brw: Drop misguided sign extension attempts in extract_imm()",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "580e1c592d90392a30185d8059499498748909fd",
"notes": null

11
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -1740,16 +1740,7 @@ extract_imm(brw_reg val, brw_reg_type type, unsigned offset)
assert(bitsize < brw_type_size_bits(val.type));
switch (val.type) {
case BRW_TYPE_UD:
val.ud = (val.ud >> (bitsize * offset)) & ((1u << bitsize) - 1);
break;
case BRW_TYPE_D:
val.d = (val.d << (bitsize * (32/bitsize - 1 - offset))) >> ((32/bitsize - 1) * bitsize);
break;
default:
return brw_reg();
}
val.ud = (val.ud >> (bitsize * offset)) & ((1u << bitsize) - 1);
return val;
}