fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-20 13:10:24 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/blorp/gen6: Prepare vertex buffer setup logic for gen8

Browse source 
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2015-03-06 14:21:25 +02:00
parent 395abb9c3b
commit 135f00e666
1 changed files with 22 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View file

@ -95,19 +95,33 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
if (brw->gen == 7)
switch (brw->gen) {
case 7:
dw0 |= GEN7_MOCS_L3 << 16;
break;
case 8:
dw0 |= BDW_MOCS_WB << 16;
break;
case 9:
dw0 |= SKL_MOCS_WB << 16;
break;
}
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
OUT_BATCH(dw0);
/* start address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
vertex_offset);
/* end address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
vertex_offset + vbo_size - 1);
OUT_BATCH(0);
if (brw->gen >= 8) {
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, vertex_offset);
OUT_BATCH(vbo_size);
} else {
/* start address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
vertex_offset);
/* end address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
vertex_offset + vbo_size - 1);
OUT_BATCH(0);
}
ADVANCE_BATCH();
}