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iris: Handle aux map init for copy engine

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We don't setup any state for the copy engine but platforms that supports
aux map, we need to init the aux map at context creation in order to
support compression.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9231

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>
This commit is contained in:
Sagar Ghuge 2023-11-28 15:37:54 -08:00 • committed by Marge Bot
parent 46f5359238
commit 135a7d5031
3 changed files with 38 additions and 7 deletions
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1
src/gallium/drivers/iris/iris_context.c
View file

@ -376,6 +376,7 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
screen->vtbl.init_copy_context(&ice->batches[IRIS_BATCH_BLITTER]);
if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
return ctx;

1
src/gallium/drivers/iris/iris_screen.h
View file

@ -63,6 +63,7 @@ struct iris_vtable {
void (*destroy_state)(struct iris_context *ice);
void (*init_render_context)(struct iris_batch *batch);
void (*init_compute_context)(struct iris_batch *batch);
void (*init_copy_context)(struct iris_batch *batch);
void (*upload_render_state)(struct iris_context *ice,
struct iris_batch *batch,
const struct pipe_draw_info *draw,

43
src/gallium/drivers/iris/iris_state.c
View file

@ -1430,6 +1430,18 @@ iris_init_compute_context(struct iris_batch *batch)
iris_batch_sync_region_end(batch);
}
static void
iris_init_copy_context(struct iris_batch *batch)
{
iris_batch_sync_region_start(batch);
#if GFX_VER >= 12
init_aux_map_state(batch);
#endif
iris_batch_sync_region_end(batch);
}
struct iris_vertex_buffer_state {
/** The VERTEX_BUFFER_STATE hardware structure. */
uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
@ -6195,14 +6207,30 @@ init_aux_map_state(struct iris_batch *batch)
uint64_t base_addr = intel_aux_map_get_base(aux_map_ctx);
assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr);
bool use_compute_reg = batch->name == IRIS_BATCH_COMPUTE &&
devinfo->has_compute_engine &&
debug_get_bool_option("INTEL_COMPUTE_CLASS", false);
uint32_t reg = 0;
switch (batch->name) {
case IRIS_BATCH_COMPUTE:
if (devinfo->has_compute_engine &&
debug_get_bool_option("INTEL_COMPUTE_CLASS", false)) {
reg = GENX(COMPCS0_AUX_TABLE_BASE_ADDR_num);
break;
}
/* fallthrough */
FALLTHROUGH;
case IRIS_BATCH_RENDER:
reg = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
break;
case IRIS_BATCH_BLITTER:
#if GFX_VERx10 >= 125
reg = GENX(BCS_AUX_TABLE_BASE_ADDR_num);
#endif
break;
default:
unreachable("Invalid batch for aux map init.");
}
uint32_t reg = use_compute_reg ? GENX(COMPCS0_AUX_TABLE_BASE_ADDR_num) :
GENX(GFX_AUX_TABLE_BASE_ADDR_num);
iris_load_register_imm64(batch, reg, base_addr);
if (reg)
iris_load_register_imm64(batch, reg, base_addr);
}
#endif
@ -9875,6 +9903,7 @@ genX(init_screen_state)(struct iris_screen *screen)
screen->vtbl.destroy_state = iris_destroy_state;
screen->vtbl.init_render_context = iris_init_render_context;
screen->vtbl.init_compute_context = iris_init_compute_context;
screen->vtbl.init_copy_context = iris_init_copy_context;
screen->vtbl.upload_render_state = iris_upload_render_state;
screen->vtbl.upload_indirect_render_state = iris_upload_indirect_render_state;
screen->vtbl.update_binder_address = iris_update_binder_address;