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i965/ir/vec4: Refactor visit(ir_texture *ir)
Splitted in two. The emission is moved to a new vec4_visitor method, vec4_visitor::emit_texture, ir order to be reused on the nir path. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This commit is contained in:
Alejandro Piñeiro
Jason Ekstrand
parent
0d43d27df7
commit
1343f403b2
2 changed files with 209 additions and 173 deletions
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@ -333,6 +333,20 @@ public:
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void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
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void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
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void emit_texture(ir_texture_opcode op,
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dst_reg dest,
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const glsl_type *dest_type,
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src_reg coordinate,
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int coord_components,
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src_reg shadow_comparitor,
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src_reg lod, src_reg lod2,
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src_reg sample_index,
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uint32_t constant_offset,
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src_reg offset_value,
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src_reg mcs,
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bool is_cube_array,
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uint32_t sampler, src_reg sampler_reg);
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uint32_t gather_channel(unsigned gather_component, uint32_t sampler);
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src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
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src_reg sampler);
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@ -2519,6 +2519,183 @@ vec4_visitor::is_high_sampler(src_reg sampler)
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return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
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}
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void
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vec4_visitor::emit_texture(ir_texture_opcode op,
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dst_reg dest,
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const glsl_type *dest_type,
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src_reg coordinate,
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int coord_components,
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src_reg shadow_comparitor,
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src_reg lod, src_reg lod2,
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src_reg sample_index,
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uint32_t constant_offset,
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src_reg offset_value,
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src_reg mcs,
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bool is_cube_array,
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uint32_t sampler,
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src_reg sampler_reg)
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{
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enum opcode opcode;
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switch (op) {
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case ir_tex: opcode = SHADER_OPCODE_TXL; break;
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case ir_txl: opcode = SHADER_OPCODE_TXL; break;
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case ir_txd: opcode = SHADER_OPCODE_TXD; break;
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case ir_txf: opcode = SHADER_OPCODE_TXF; break;
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case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
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case ir_txs: opcode = SHADER_OPCODE_TXS; break;
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case ir_tg4: opcode = offset_value.file != BAD_FILE
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? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
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case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
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case ir_txb:
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unreachable("TXB is not valid for vertex shaders.");
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case ir_lod:
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unreachable("LOD is not valid for vertex shaders.");
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default:
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unreachable("Unrecognized tex op");
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}
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vec4_instruction *inst = new(mem_ctx) vec4_instruction(
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opcode, dst_reg(this, dest_type));
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inst->offset = constant_offset;
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/* The message header is necessary for:
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* - Gen4 (always)
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* - Gen9+ for selecting SIMD4x2
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* - Texel offsets
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* - Gather channel selection
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* - Sampler indices too large to fit in a 4-bit value.
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*/
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inst->header_size =
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(devinfo->gen < 5 || devinfo->gen >= 9 ||
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inst->offset != 0 || op == ir_tg4 ||
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is_high_sampler(sampler_reg)) ? 1 : 0;
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inst->base_mrf = 2;
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inst->mlen = inst->header_size + 1; /* always at least one */
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inst->dst.writemask = WRITEMASK_XYZW;
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inst->shadow_compare = shadow_comparitor.file != BAD_FILE;
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inst->src[1] = sampler_reg;
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/* MRF for the first parameter */
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int param_base = inst->base_mrf + inst->header_size;
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if (op == ir_txs || op == ir_query_levels) {
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int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
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emit(MOV(dst_reg(MRF, param_base, lod.type, writemask), lod));
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} else {
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/* Load the coordinate */
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/* FINISHME: gl_clamp_mask and saturate */
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int coord_mask = (1 << coord_components) - 1;
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int zero_mask = 0xf & ~coord_mask;
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emit(MOV(dst_reg(MRF, param_base, coordinate.type, coord_mask),
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coordinate));
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if (zero_mask != 0) {
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emit(MOV(dst_reg(MRF, param_base, coordinate.type, zero_mask),
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src_reg(0)));
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}
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/* Load the shadow comparitor */
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if (shadow_comparitor.file != BAD_FILE && op != ir_txd && (op != ir_tg4 || offset_value.file == BAD_FILE)) {
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emit(MOV(dst_reg(MRF, param_base + 1, shadow_comparitor.type,
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WRITEMASK_X),
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shadow_comparitor));
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inst->mlen++;
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}
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/* Load the LOD info */
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if (op == ir_tex || op == ir_txl) {
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int mrf, writemask;
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if (devinfo->gen >= 5) {
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mrf = param_base + 1;
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if (shadow_comparitor.file != BAD_FILE) {
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writemask = WRITEMASK_Y;
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/* mlen already incremented */
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} else {
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writemask = WRITEMASK_X;
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inst->mlen++;
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}
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} else /* devinfo->gen == 4 */ {
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mrf = param_base;
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writemask = WRITEMASK_W;
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}
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lod.swizzle = BRW_SWIZZLE_XXXX;
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emit(MOV(dst_reg(MRF, mrf, lod.type, writemask), lod));
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} else if (op == ir_txf) {
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emit(MOV(dst_reg(MRF, param_base, lod.type, WRITEMASK_W), lod));
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} else if (op == ir_txf_ms) {
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emit(MOV(dst_reg(MRF, param_base + 1, sample_index.type, WRITEMASK_X),
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sample_index));
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if (devinfo->gen >= 7) {
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/* MCS data is in the first channel of `mcs`, but we need to get it into
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* the .y channel of the second vec4 of params, so replicate .x across
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* the whole vec4 and then mask off everything except .y
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*/
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mcs.swizzle = BRW_SWIZZLE_XXXX;
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emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
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mcs));
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}
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inst->mlen++;
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} else if (op == ir_txd) {
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const brw_reg_type type = lod.type;
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if (devinfo->gen >= 5) {
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lod.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
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lod2.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), lod));
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), lod2));
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inst->mlen++;
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if (dest_type->vector_elements == 3 || shadow_comparitor.file != BAD_FILE) {
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lod.swizzle = BRW_SWIZZLE_ZZZZ;
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lod2.swizzle = BRW_SWIZZLE_ZZZZ;
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), lod));
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), lod2));
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inst->mlen++;
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if (shadow_comparitor.file != BAD_FILE) {
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emit(MOV(dst_reg(MRF, param_base + 2,
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shadow_comparitor.type, WRITEMASK_Z),
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shadow_comparitor));
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}
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}
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} else /* devinfo->gen == 4 */ {
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), lod));
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), lod2));
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inst->mlen += 2;
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}
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} else if (op == ir_tg4 && offset_value.file != BAD_FILE) {
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if (shadow_comparitor.file != BAD_FILE) {
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emit(MOV(dst_reg(MRF, param_base, shadow_comparitor.type, WRITEMASK_W),
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shadow_comparitor));
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}
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emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::ivec2_type, WRITEMASK_XY),
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offset_value));
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inst->mlen++;
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}
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}
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emit(inst);
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/* fixup num layers (z) for cube arrays: hardware returns faces * layers;
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* spec requires layers.
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*/
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if (op == ir_txs && is_cube_array) {
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emit_math(SHADER_OPCODE_INT_QUOTIENT,
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writemask(inst->dst, WRITEMASK_Z),
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src_reg(inst->dst), src_reg(6));
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}
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if (devinfo->gen == 6 && op == ir_tg4) {
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emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], inst->dst);
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}
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swizzle_result(op, dest,
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src_reg(inst->dst), sampler, dest_type);
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}
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void
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vec4_visitor::visit(ir_texture *ir)
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{
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@ -2584,7 +2761,9 @@ vec4_visitor::visit(ir_texture *ir)
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* generating these values may involve SEND messages that need the MRFs.
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*/
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src_reg coordinate;
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int coord_components = 0;
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if (ir->coordinate) {
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coord_components = ir->coordinate->type->vector_elements;
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ir->coordinate->accept(this);
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coordinate = this->result;
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}
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@ -2602,28 +2781,23 @@ vec4_visitor::visit(ir_texture *ir)
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offset_value = src_reg(this->result);
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}
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const glsl_type *lod_type = NULL, *sample_index_type = NULL;
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src_reg lod, dPdx, dPdy, sample_index, mcs;
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src_reg lod, lod2, sample_index, mcs;
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switch (ir->op) {
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case ir_tex:
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lod = src_reg(0.0f);
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lod_type = glsl_type::float_type;
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break;
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case ir_txf:
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case ir_txl:
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case ir_txs:
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ir->lod_info.lod->accept(this);
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lod = this->result;
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lod_type = ir->lod_info.lod->type;
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break;
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case ir_query_levels:
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lod = src_reg(0);
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lod_type = glsl_type::int_type;
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break;
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case ir_txf_ms:
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ir->lod_info.sample_index->accept(this);
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sample_index = this->result;
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sample_index_type = ir->lod_info.sample_index->type;
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if (devinfo->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
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mcs = emit_mcs_fetch(ir->coordinate->type, coordinate, sampler_reg);
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@ -2632,12 +2806,10 @@ vec4_visitor::visit(ir_texture *ir)
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break;
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case ir_txd:
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ir->lod_info.grad.dPdx->accept(this);
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dPdx = this->result;
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lod = this->result;
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ir->lod_info.grad.dPdy->accept(this);
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dPdy = this->result;
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lod_type = ir->lod_info.grad.dPdx->type;
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lod2 = this->result;
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break;
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case ir_txb:
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case ir_lod:
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@ -2645,181 +2817,31 @@ vec4_visitor::visit(ir_texture *ir)
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break;
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}
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enum opcode opcode;
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switch (ir->op) {
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case ir_tex: opcode = SHADER_OPCODE_TXL; break;
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case ir_txl: opcode = SHADER_OPCODE_TXL; break;
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case ir_txd: opcode = SHADER_OPCODE_TXD; break;
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case ir_txf: opcode = SHADER_OPCODE_TXF; break;
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case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
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case ir_txs: opcode = SHADER_OPCODE_TXS; break;
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case ir_tg4: opcode = has_nonconstant_offset
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? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
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case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
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case ir_txb:
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unreachable("TXB is not valid for vertex shaders.");
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case ir_lod:
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unreachable("LOD is not valid for vertex shaders.");
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default:
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unreachable("Unrecognized tex op");
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}
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vec4_instruction *inst = new(mem_ctx) vec4_instruction(
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opcode, dst_reg(this, ir->type));
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uint32_t constant_offset = 0;
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if (ir->offset != NULL && !has_nonconstant_offset) {
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inst->offset =
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constant_offset =
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brw_texture_offset(ir->offset->as_constant()->value.i,
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ir->offset->type->vector_elements);
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}
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/* Stuff the channel select bits in the top of the texture offset */
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if (ir->op == ir_tg4)
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inst->offset |=
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gather_channel( ir->lod_info.component->as_constant()->value.i[0],
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sampler) << 16;
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constant_offset |=
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gather_channel( ir->lod_info.component->as_constant()->value.i[0],
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sampler) << 16;
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/* The message header is necessary for:
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* - Gen4 (always)
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* - Gen9+ for selecting SIMD4x2
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* - Texel offsets
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* - Gather channel selection
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* - Sampler indices too large to fit in a 4-bit value.
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*/
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inst->header_size =
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(devinfo->gen < 5 || devinfo->gen >= 9 ||
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inst->offset != 0 || ir->op == ir_tg4 ||
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is_high_sampler(sampler_reg)) ? 1 : 0;
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inst->base_mrf = 2;
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inst->mlen = inst->header_size + 1; /* always at least one */
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inst->dst.writemask = WRITEMASK_XYZW;
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inst->shadow_compare = ir->shadow_comparitor != NULL;
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inst->src[1] = sampler_reg;
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/* MRF for the first parameter */
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int param_base = inst->base_mrf + inst->header_size;
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if (ir->op == ir_txs || ir->op == ir_query_levels) {
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int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
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emit(MOV(dst_reg(MRF, param_base, lod_type, writemask), lod));
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} else {
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/* Load the coordinate */
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/* FINISHME: gl_clamp_mask and saturate */
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int coord_mask = (1 << ir->coordinate->type->vector_elements) - 1;
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int zero_mask = 0xf & ~coord_mask;
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emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, coord_mask),
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coordinate));
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if (zero_mask != 0) {
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emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, zero_mask),
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src_reg(0)));
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}
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/* Load the shadow comparitor */
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if (ir->shadow_comparitor && ir->op != ir_txd && (ir->op != ir_tg4 || !has_nonconstant_offset)) {
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emit(MOV(dst_reg(MRF, param_base + 1, ir->shadow_comparitor->type,
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WRITEMASK_X),
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shadow_comparitor));
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inst->mlen++;
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}
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/* Load the LOD info */
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if (ir->op == ir_tex || ir->op == ir_txl) {
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int mrf, writemask;
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if (devinfo->gen >= 5) {
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mrf = param_base + 1;
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if (ir->shadow_comparitor) {
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writemask = WRITEMASK_Y;
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/* mlen already incremented */
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} else {
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writemask = WRITEMASK_X;
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inst->mlen++;
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}
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} else /* devinfo->gen == 4 */ {
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mrf = param_base;
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writemask = WRITEMASK_W;
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}
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emit(MOV(dst_reg(MRF, mrf, lod_type, writemask), lod));
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} else if (ir->op == ir_txf) {
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emit(MOV(dst_reg(MRF, param_base, lod_type, WRITEMASK_W), lod));
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} else if (ir->op == ir_txf_ms) {
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emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
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sample_index));
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if (devinfo->gen >= 7) {
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/* MCS data is in the first channel of `mcs`, but we need to get it into
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* the .y channel of the second vec4 of params, so replicate .x across
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* the whole vec4 and then mask off everything except .y
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*/
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mcs.swizzle = BRW_SWIZZLE_XXXX;
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emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
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mcs));
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}
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inst->mlen++;
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} else if (ir->op == ir_txd) {
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const glsl_type *type = lod_type;
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if (devinfo->gen >= 5) {
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dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
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dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), dPdx));
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), dPdy));
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inst->mlen++;
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if (ir->type->vector_elements == 3 || ir->shadow_comparitor) {
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dPdx.swizzle = BRW_SWIZZLE_ZZZZ;
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dPdy.swizzle = BRW_SWIZZLE_ZZZZ;
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), dPdx));
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), dPdy));
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inst->mlen++;
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||||
|
||||
if (ir->shadow_comparitor) {
|
||||
emit(MOV(dst_reg(MRF, param_base + 2,
|
||||
ir->shadow_comparitor->type, WRITEMASK_Z),
|
||||
shadow_comparitor));
|
||||
}
|
||||
}
|
||||
} else /* devinfo->gen == 4 */ {
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));
|
||||
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), dPdy));
|
||||
inst->mlen += 2;
|
||||
}
|
||||
} else if (ir->op == ir_tg4 && has_nonconstant_offset) {
|
||||
if (ir->shadow_comparitor) {
|
||||
emit(MOV(dst_reg(MRF, param_base, ir->shadow_comparitor->type, WRITEMASK_W),
|
||||
shadow_comparitor));
|
||||
}
|
||||
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::ivec2_type, WRITEMASK_XY),
|
||||
offset_value));
|
||||
inst->mlen++;
|
||||
}
|
||||
}
|
||||
|
||||
emit(inst);
|
||||
|
||||
/* fixup num layers (z) for cube arrays: hardware returns faces * layers;
|
||||
* spec requires layers.
|
||||
*/
|
||||
if (ir->op == ir_txs) {
|
||||
glsl_type const *type = ir->sampler->type;
|
||||
if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
|
||||
type->sampler_array) {
|
||||
emit_math(SHADER_OPCODE_INT_QUOTIENT,
|
||||
writemask(inst->dst, WRITEMASK_Z),
|
||||
src_reg(inst->dst), src_reg(6));
|
||||
}
|
||||
}
|
||||
|
||||
if (devinfo->gen == 6 && ir->op == ir_tg4) {
|
||||
emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], inst->dst);
|
||||
}
|
||||
glsl_type const *type = ir->sampler->type;
|
||||
bool is_cube_array = type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
|
||||
type->sampler_array;
|
||||
|
||||
this->result = src_reg(this, ir->type);
|
||||
dst_reg dest = dst_reg(this->result);
|
||||
|
||||
swizzle_result(ir->op, dest, src_reg(inst->dst),
|
||||
sampler, ir->type);
|
||||
emit_texture(ir->op, dest, ir->type, coordinate, coord_components,
|
||||
shadow_comparitor,
|
||||
lod, lod2, sample_index,
|
||||
constant_offset, offset_value,
|
||||
mcs, is_cube_array, sampler, sampler_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue