diff --git a/src/amd/vulkan/meta/radv_meta_blit.c b/src/amd/vulkan/meta/radv_meta_blit.c
index e366a130634..a9002ea9066 100644
--- a/src/amd/vulkan/meta/radv_meta_blit.c
+++ b/src/amd/vulkan/meta/radv_meta_blit.c
@@ -86,17 +86,17 @@ get_pipeline(struct radv_device *device, const struct radv_image_view *src_iview
    }
 
    nir_shader *fs;
-   nir_shader *vs = radv_meta_nir_build_blit_vertex_shader(device);
+   nir_shader *vs = radv_meta_nir_build_blit_vertex_shader();
 
    switch (aspect) {
    case VK_IMAGE_ASPECT_COLOR_BIT:
-      fs = radv_meta_nir_build_blit_copy_fragment_shader(device, tex_dim);
+      fs = radv_meta_nir_build_blit_copy_fragment_shader(tex_dim);
       break;
    case VK_IMAGE_ASPECT_DEPTH_BIT:
-      fs = radv_meta_nir_build_blit_copy_fragment_shader_depth(device, tex_dim);
+      fs = radv_meta_nir_build_blit_copy_fragment_shader_depth(tex_dim);
       break;
    case VK_IMAGE_ASPECT_STENCIL_BIT:
-      fs = radv_meta_nir_build_blit_copy_fragment_shader_stencil(device, tex_dim);
+      fs = radv_meta_nir_build_blit_copy_fragment_shader_stencil(tex_dim);
       break;
    default:
       UNREACHABLE("Unhandled aspect");
diff --git a/src/amd/vulkan/meta/radv_meta_blit2d.c b/src/amd/vulkan/meta/radv_meta_blit2d.c
index a7016914c44..9bf5de88e6f 100644
--- a/src/amd/vulkan/meta/radv_meta_blit2d.c
+++ b/src/amd/vulkan/meta/radv_meta_blit2d.c
@@ -477,9 +477,9 @@ get_color_pipeline(struct radv_device *device, enum blit2d_src_type src_type, Vk
       break;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader(device);
+   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader();
    nir_shader *fs_module = radv_meta_nir_build_blit2d_copy_fragment_shader(
-      device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
+      src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
 
    const VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
@@ -617,9 +617,9 @@ get_depth_only_pipeline(struct radv_device *device, enum blit2d_src_type src_typ
       break;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader(device);
+   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader();
    nir_shader *fs_module = radv_meta_nir_build_blit2d_copy_fragment_shader_depth(
-      device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
+      src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
 
    const VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
@@ -775,9 +775,9 @@ get_stencil_only_pipeline(struct radv_device *device, enum blit2d_src_type src_t
       break;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader(device);
+   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader();
    nir_shader *fs_module = radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(
-      device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
+      src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
 
    const VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
@@ -924,9 +924,9 @@ get_depth_stencil_pipeline(struct radv_device *device, enum blit2d_src_type src_
       break;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader(device);
+   nir_shader *vs_module = radv_meta_nir_build_blit2d_vertex_shader();
    nir_shader *fs_module = radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(
-      device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
+      src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
 
    const VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c
index 2844504e4eb..a670b6d10b7 100644
--- a/src/amd/vulkan/meta/radv_meta_buffer.c
+++ b/src/amd/vulkan/meta/radv_meta_buffer.c
@@ -54,7 +54,7 @@ get_fill_memory_pipeline(struct radv_device *device, uint64_t size, VkPipeline *
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_fill_memory_shader(device, use_16B_copy ? 16 : 4);
+   nir_shader *cs = radv_meta_nir_build_fill_memory_shader(use_16B_copy ? 16 : 4);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -123,7 +123,7 @@ get_copy_memory_pipeline(struct radv_device *device, uint64_t src_va, uint64_t d
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_copy_memory_shader(device, use_16B_copy ? 16 : 1);
+   nir_shader *cs = radv_meta_nir_build_copy_memory_shader(use_16B_copy ? 16 : 1);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_bufimage.c b/src/amd/vulkan/meta/radv_meta_bufimage.c
index 5360f0b961b..831973c97a8 100644
--- a/src/amd/vulkan/meta/radv_meta_bufimage.c
+++ b/src/amd/vulkan/meta/radv_meta_bufimage.c
@@ -79,7 +79,7 @@ get_itob_pipeline(struct radv_device *device, const struct radv_image *image, Vk
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_itob_compute_shader(device, is_3d);
+   nir_shader *cs = radv_meta_nir_build_itob_compute_shader(is_3d);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -161,7 +161,7 @@ get_btoi_pipeline(struct radv_device *device, const struct radv_image *image, Vk
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_btoi_compute_shader(device, is_3d);
+   nir_shader *cs = radv_meta_nir_build_btoi_compute_shader(is_3d);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -254,7 +254,7 @@ get_itoi_pipeline(struct radv_device *device, const struct radv_image *src_image
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_itoi_compute_shader(device, src_3d, dst_3d, samples);
+   nir_shader *cs = radv_meta_nir_build_itoi_compute_shader(src_3d, dst_3d, samples);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -337,7 +337,7 @@ get_cleari_pipeline(struct radv_device *device, const struct radv_image *image,
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_cleari_compute_shader(device, is_3d, samples);
+   nir_shader *cs = radv_meta_nir_build_cleari_compute_shader(is_3d, samples);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -397,7 +397,7 @@ get_cleari_96bit_pipeline(struct radv_device *device, VkPipeline *pipeline_out,
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_cleari_96bit_compute_shader(device);
+   nir_shader *cs = radv_meta_nir_build_cleari_96bit_compute_shader();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c
index 39476a488e6..39600205752 100644
--- a/src/amd/vulkan/meta/radv_meta_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_clear.c
@@ -82,8 +82,7 @@ get_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t frag_o
    }
 
    nir_shader *vs_module, *fs_module;
-
-   radv_meta_nir_build_clear_color_shaders(device, &vs_module, &fs_module, frag_output);
+   radv_meta_nir_build_clear_color_shaders(&vs_module, &fs_module, frag_output);
 
    VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = {0};
    blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState){
@@ -327,7 +326,7 @@ get_depth_stencil_pipeline(struct radv_device *device, int samples, VkImageAspec
 
    nir_shader *vs_module, *fs_module;
 
-   radv_meta_nir_build_clear_depthstencil_shaders(device, &vs_module, &fs_module, unrestricted);
+   radv_meta_nir_build_clear_depthstencil_shaders(&vs_module, &fs_module, unrestricted);
 
    VkGraphicsPipelineCreateInfoRADV radv_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV,
@@ -572,7 +571,7 @@ get_clear_htile_mask_pipeline(struct radv_device *device, VkPipeline *pipeline_o
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_clear_htile_mask_shader(device);
+   nir_shader *cs = radv_meta_nir_build_clear_htile_mask_shader();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -955,7 +954,7 @@ get_clear_dcc_comp_to_single_pipeline(struct radv_device *device, bool is_msaa,
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_clear_dcc_comp_to_single_shader(device, is_msaa);
+   nir_shader *cs = radv_meta_nir_build_clear_dcc_comp_to_single_shader(is_msaa);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_clear_hiz.c b/src/amd/vulkan/meta/radv_meta_clear_hiz.c
index 268cce494a6..b055b23e00e 100644
--- a/src/amd/vulkan/meta/radv_meta_clear_hiz.c
+++ b/src/amd/vulkan/meta/radv_meta_clear_hiz.c
@@ -63,7 +63,7 @@ get_clear_hiz_pipeline(struct radv_device *device, const struct radv_image *imag
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_clear_hiz_compute_shader(device, samples);
+   nir_shader *cs = radv_meta_nir_build_clear_hiz_compute_shader(samples);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c b/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c
index 08d9a9830ea..93fc243e570 100644
--- a/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c
+++ b/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c
@@ -32,7 +32,7 @@ get_compute_copy_memory_indirect_preprocess_pipeline(struct radv_device *device,
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_copy_memory_indirect_preprocess_cs(device);
+   nir_shader *cs = radv_meta_nir_build_copy_memory_indirect_preprocess_cs();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -112,7 +112,7 @@ get_compute_copy_memory_indirect_pipeline(struct radv_device *device, VkPipeline
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_copy_memory_indirect_cs(device);
+   nir_shader *cs = radv_meta_nir_build_copy_memory_indirect_cs();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -214,7 +214,7 @@ get_compute_copy_memory_to_image_indirect_preprocess_pipeline(struct radv_device
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(device);
+   nir_shader *cs = radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -345,7 +345,7 @@ get_compute_copy_memory_to_image_indirect_pipeline(struct radv_device *device, c
    }
 
    nir_shader *cs = radv_meta_nir_build_copy_memory_to_image_indirect_cs(
-      device, key.fmt_block_width, key.fmt_block_height, key.fmt_block_depth, key.fmt_element_size_B, key.is_3d);
+      key.fmt_block_width, key.fmt_block_height, key.fmt_block_depth, key.fmt_element_size_B, key.is_3d);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c b/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c
index 0276f864ac1..6fc9572cb14 100644
--- a/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c
+++ b/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c
@@ -64,9 +64,9 @@ get_gfx_copy_memory_to_image_indirect_pipeline(struct radv_device *device, const
    }
 
    nir_shader *vs_module = radv_meta_nir_build_copy_memory_to_image_indirect_vs(
-      device, key.fmt_block_width, key.fmt_block_height, key.fmt_block_depth);
+      key.fmt_block_width, key.fmt_block_height, key.fmt_block_depth);
    nir_shader *fs_module = radv_meta_nir_build_copy_memory_to_image_indirect_fs(
-      device, aspect_mask, key.fmt_block_width, key.fmt_block_height, key.fmt_element_size_B);
+      aspect_mask, key.fmt_block_width, key.fmt_block_height, key.fmt_element_size_B);
 
    VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
index 86b3e07e97b..bb3f71b4e77 100644
--- a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
+++ b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
@@ -49,7 +49,7 @@ get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *p
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_copy_vrs_htile_shader(device, pdev->info.gfx_level, pdev->info.gb_addr_config,
+   nir_shader *cs = radv_meta_nir_build_copy_vrs_htile_shader(pdev->info.gfx_level, pdev->info.gb_addr_config,
                                                               &image->planes[0].surface);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
diff --git a/src/amd/vulkan/meta/radv_meta_dcc_retile.c b/src/amd/vulkan/meta/radv_meta_dcc_retile.c
index faffcc9dc99..43a421a8c3d 100644
--- a/src/amd/vulkan/meta/radv_meta_dcc_retile.c
+++ b/src/amd/vulkan/meta/radv_meta_dcc_retile.c
@@ -82,8 +82,8 @@ get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *p
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_dcc_retile_compute_shader(device, pdev->info.gfx_level,
-                                                                  pdev->info.gb_addr_config, &image->planes[0].surface);
+   nir_shader *cs = radv_meta_nir_build_dcc_retile_compute_shader(pdev->info.gfx_level, pdev->info.gb_addr_config,
+                                                                  &image->planes[0].surface);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c
index 640f743a107..40fecc643e7 100644
--- a/src/amd/vulkan/meta/radv_meta_decompress.c
+++ b/src/amd/vulkan/meta/radv_meta_decompress.c
@@ -38,8 +38,8 @@ get_pipeline_gfx(struct radv_device *device, struct radv_image *image, VkPipelin
       return VK_SUCCESS;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
-   nir_shader *fs_module = radv_meta_nir_build_fs_noop(device);
+   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices();
+   nir_shader *fs_module = radv_meta_nir_build_fs_noop();
 
    const VkPipelineSampleLocationsStateCreateInfoEXT sample_locs_create_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT,
@@ -299,7 +299,7 @@ get_pipeline_cs(struct radv_device *device, VkPipeline *pipeline_out, VkPipeline
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_expand_depth_stencil_compute_shader(device);
+   nir_shader *cs = radv_meta_nir_build_expand_depth_stencil_compute_shader();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c
index cd60f94aab2..b8657e91597 100644
--- a/src/amd/vulkan/meta/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c
@@ -56,7 +56,7 @@ get_dcc_decompress_compute_pipeline(struct radv_device *device, VkPipeline *pipe
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_dcc_decompress_compute_shader(device);
+   nir_shader *cs = radv_meta_nir_build_dcc_decompress_compute_shader();
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -109,8 +109,8 @@ get_pipeline(struct radv_device *device, enum radv_color_op op, VkPipeline *pipe
       return VK_SUCCESS;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
-   nir_shader *fs_module = radv_meta_nir_build_fs_noop(device);
+   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices();
+   nir_shader *fs_module = radv_meta_nir_build_fs_noop();
 
    VkGraphicsPipelineCreateInfoRADV radv_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV,
diff --git a/src/amd/vulkan/meta/radv_meta_fmask_copy.c b/src/amd/vulkan/meta/radv_meta_fmask_copy.c
index 8c6426b6c52..c4a89dbe524 100644
--- a/src/amd/vulkan/meta/radv_meta_fmask_copy.c
+++ b/src/amd/vulkan/meta/radv_meta_fmask_copy.c
@@ -65,7 +65,7 @@ get_pipeline(struct radv_device *device, uint32_t samples_log2, VkPipeline *pipe
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_fmask_copy_compute_shader(device, samples);
+   nir_shader *cs = radv_meta_nir_build_fmask_copy_compute_shader(samples);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_fmask_expand.c b/src/amd/vulkan/meta/radv_meta_fmask_expand.c
index a9326e4b878..0d95e1b62ee 100644
--- a/src/amd/vulkan/meta/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/meta/radv_meta_fmask_expand.c
@@ -67,7 +67,7 @@ get_pipeline(struct radv_device *device, uint32_t samples_log2, VkPipeline *pipe
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_fmask_expand_compute_shader(device, samples);
+   nir_shader *cs = radv_meta_nir_build_fmask_expand_compute_shader(samples);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
index 8187b7c8373..105016a3512 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
@@ -109,8 +109,8 @@ get_compute_resolve_pipeline(struct radv_device *device, VkFormat format, int sa
       return VK_SUCCESS;
    }
 
-   nir_shader *cs = radv_meta_nir_build_resolve_cs(device, pdev->use_fmask, key.resolve_type, key.samples, key.aspects,
-                                                   key.resolve_mode);
+   nir_shader *cs =
+      radv_meta_nir_build_resolve_cs(pdev->use_fmask, key.resolve_type, key.samples, key.aspects, key.resolve_mode);
 
    const VkPipelineShaderStageCreateInfo stage_info = {
       .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
index 6408a227089..ed5e6deac27 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
@@ -75,9 +75,9 @@ get_gfx_resolve_pipeline(struct radv_device *device, VkFormat format, int sample
       return VK_SUCCESS;
    }
 
-   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
-   nir_shader *fs_module = radv_meta_nir_build_resolve_fs(device, pdev->use_fmask, key.samples,
-                                                          vk_format_is_int(key.format), key.aspects, key.resolve_mode);
+   nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices();
+   nir_shader *fs_module = radv_meta_nir_build_resolve_fs(pdev->use_fmask, key.samples, vk_format_is_int(key.format),
+                                                          key.aspects, key.resolve_mode);
 
    VkGraphicsPipelineCreateInfo pipeline_create_info = {
       .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
diff --git a/src/amd/vulkan/nir/radv_meta_nir.c b/src/amd/vulkan/nir/radv_meta_nir.c
index 412802f32fc..a4c4ac47769 100644
--- a/src/amd/vulkan/nir/radv_meta_nir.c
+++ b/src/amd/vulkan/nir/radv_meta_nir.c
@@ -12,11 +12,8 @@
 #include "ac_nir_surface.h"
 #include "ac_surface.h"
 #include "nir_builder.h"
-#include "radv_device.h"
-#include "radv_physical_device.h"
 
-nir_builder PRINTFLIKE(3, 4)
-   radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...)
+nir_builder PRINTFLIKE(2, 3) radv_meta_nir_init_shader(mesa_shader_stage stage, const char *name, ...)
 {
    nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);
    if (name) {
@@ -31,13 +28,13 @@ nir_builder PRINTFLIKE(3, 4)
 
 /* vertex shader that generates vertices */
 nir_shader *
-radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev)
+radv_meta_nir_build_vs_generate_vertices()
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
 
    nir_variable *v_position;
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_vs_gen_verts");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_VERTEX, "meta_vs_gen_verts");
 
    nir_def *outvec = nir_gen_rect_vertices(&b, NULL, NULL);
 
@@ -50,9 +47,9 @@ radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev)
 }
 
 nir_shader *
-radv_meta_nir_build_fs_noop(struct radv_device *dev)
+radv_meta_nir_build_fs_noop()
 {
-   return radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
+   return radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
 }
 
 static void
@@ -139,11 +136,11 @@ radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
 }
 
 nir_shader *
-radv_meta_nir_build_fill_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation)
+radv_meta_nir_build_fill_memory_shader(uint32_t bytes_per_invocation)
 {
    assert(bytes_per_invocation == 4 || bytes_per_invocation == 16);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fill_memory_%dB", bytes_per_invocation);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_fill_memory_%dB", bytes_per_invocation);
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *pconst = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 16);
@@ -163,14 +160,14 @@ radv_meta_nir_build_fill_memory_shader(struct radv_device *dev, uint32_t bytes_p
 }
 
 nir_shader *
-radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation)
+radv_meta_nir_build_copy_memory_shader(uint32_t bytes_per_invocation)
 {
    assert(bytes_per_invocation == 1 || bytes_per_invocation == 16);
 
    const uint32_t num_components = bytes_per_invocation == 1 ? 1 : 4;
    const uint32_t bit_size = bytes_per_invocation == 1 ? 8 : 32;
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_copy_memory_%dB", bytes_per_invocation);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_copy_memory_%dB", bytes_per_invocation);
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *pconst = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 16);
@@ -192,10 +189,10 @@ radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_p
 }
 
 nir_shader *
-radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev)
+radv_meta_nir_build_blit_vertex_shader()
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_blit_vs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_VERTEX, "meta_blit_vs");
 
    nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
    pos_out->data.location = VARYING_SLOT_POS;
@@ -234,10 +231,10 @@ radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev)
 }
 
 nir_shader *
-radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
+radv_meta_nir_build_blit_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -266,10 +263,10 @@ radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl
 }
 
 nir_shader *
-radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
+radv_meta_nir_build_blit_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -298,10 +295,10 @@ radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enu
 }
 
 nir_shader *
-radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
+radv_meta_nir_build_blit_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -330,11 +327,11 @@ radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev, e
 }
 
 nir_shader *
-radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device)
+radv_meta_nir_build_blit2d_vertex_shader()
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_VERTEX, "meta_blit2d_vs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_VERTEX, "meta_blit2d_vs");
 
    nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
    pos_out->data.location = VARYING_SLOT_POS;
@@ -415,13 +412,12 @@ radv_meta_nir_build_blit2d_buffer_fetch(nir_builder *b, uint32_t binding, nir_de
 }
 
 nir_shader *
-radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
-                                                radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
+radv_meta_nir_build_blit2d_copy_fragment_shader(radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
                                                 bool is_3d, bool is_multisampled)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -441,13 +437,12 @@ radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
 }
 
 nir_shader *
-radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device,
-                                                      radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
+radv_meta_nir_build_blit2d_copy_fragment_shader_depth(radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
                                                       bool is_3d, bool is_multisampled)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -467,13 +462,12 @@ radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device
 }
 
 nir_shader *
-radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *device,
-                                                        radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
+radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(radv_meta_nir_texel_fetch_build_func txf_func, const char *name,
                                                         bool is_3d, bool is_multisampled)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -493,13 +487,12 @@ radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *devi
 }
 
 nir_shader *
-radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(struct radv_device *device,
-                                                              radv_meta_nir_texel_fetch_build_func txf_func,
+radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(radv_meta_nir_texel_fetch_build_func txf_func,
                                                               const char *name, bool is_3d, bool is_multisampled)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -526,12 +519,12 @@ radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(struct radv_device
 }
 
 nir_shader *
-radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d)
+radv_meta_nir_build_itob_compute_shader(bool is_3d)
 {
    enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *sampler_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
    nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
@@ -566,12 +559,12 @@ radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d)
 }
 
 nir_shader *
-radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d)
+radv_meta_nir_build_btoi_compute_shader(bool is_3d)
 {
    enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
    const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
    nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
@@ -606,7 +599,7 @@ radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d)
 }
 
 nir_shader *
-radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bool dst_3d, int samples)
+radv_meta_nir_build_itoi_compute_shader(bool src_3d, bool dst_3d, int samples)
 {
    bool is_multisampled = samples > 1;
    enum glsl_sampler_dim src_dim = src_3d            ? GLSL_SAMPLER_DIM_3D
@@ -617,7 +610,7 @@ radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bo
                                                      : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *buf_type = glsl_sampler_type(src_dim, false, false, GLSL_TYPE_FLOAT);
    const struct glsl_type *img_type = glsl_image_type(dst_dim, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_cs-%dd-%dd-%d", src_3d ? 3 : 2,
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_itoi_cs-%dd-%dd-%d", src_3d ? 3 : 2,
                                              dst_3d ? 3 : 2, samples);
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
@@ -661,15 +654,15 @@ radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bo
 }
 
 nir_shader *
-radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples)
+radv_meta_nir_build_cleari_compute_shader(bool is_3d, int samples)
 {
    bool is_multisampled = samples > 1;
    enum glsl_sampler_dim dim = is_3d             ? GLSL_SAMPLER_DIM_3D
                                : is_multisampled ? GLSL_SAMPLER_DIM_MS
                                                  : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE,
-                                             is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
+   nir_builder b =
+      radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -699,10 +692,10 @@ radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, i
 
 /** Special path for clearing 96bit images using a compute shader. */
 nir_shader *
-radv_meta_nir_build_cleari_96bit_compute_shader(struct radv_device *dev)
+radv_meta_nir_build_cleari_96bit_compute_shader()
 {
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_cleari_96bit_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_cleari_96bit_cs");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -733,11 +726,10 @@ radv_meta_nir_build_cleari_96bit_compute_shader(struct radv_device *dev)
 }
 
 void
-radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs, struct nir_shader **out_fs,
-                                        uint32_t frag_output)
+radv_meta_nir_build_clear_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs, uint32_t frag_output)
 {
-   nir_builder vs_b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_clear_color_vs");
-   nir_builder fs_b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
+   nir_builder vs_b = radv_meta_nir_init_shader(MESA_SHADER_VERTEX, "meta_clear_color_vs");
+   nir_builder fs_b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
 
    const struct glsl_type *position_type = glsl_vec4_type();
    const struct glsl_type *color_type = glsl_vec4_type();
@@ -770,14 +762,13 @@ radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shad
 }
 
 void
-radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
-                                               struct nir_shader **out_fs, bool unrestricted)
+radv_meta_nir_build_clear_depthstencil_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs,
+                                               bool unrestricted)
 {
    nir_builder vs_b = radv_meta_nir_init_shader(
-      dev, MESA_SHADER_VERTEX, unrestricted ? "meta_clear_depthstencil_unrestricted_vs" : "meta_clear_depthstencil_vs");
+      MESA_SHADER_VERTEX, unrestricted ? "meta_clear_depthstencil_unrestricted_vs" : "meta_clear_depthstencil_vs");
    nir_builder fs_b = radv_meta_nir_init_shader(
-      dev, MESA_SHADER_FRAGMENT,
-      unrestricted ? "meta_clear_depthstencil_unrestricted_fs" : "meta_clear_depthstencil_fs");
+      MESA_SHADER_FRAGMENT, unrestricted ? "meta_clear_depthstencil_unrestricted_fs" : "meta_clear_depthstencil_fs");
 
    const struct glsl_type *position_out_type = glsl_vec4_type();
 
@@ -815,9 +806,9 @@ radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct n
 }
 
 nir_shader *
-radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev)
+radv_meta_nir_build_clear_htile_mask_shader()
 {
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *global_id = radv_meta_nir_get_global_ids(&b, 1);
@@ -845,12 +836,12 @@ radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev)
  * For MSAA images, clearing the first sample should be enough as long as CMASK is also cleared.
  */
 nir_shader *
-radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa)
+radv_meta_nir_build_clear_dcc_comp_to_single_shader(bool is_msaa)
 {
    enum glsl_sampler_dim dim = is_msaa ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *img_type = glsl_image_type(dim, true, GLSL_TYPE_FLOAT);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
                                              is_msaa ? "multisampled" : "singlesampled");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
@@ -885,10 +876,10 @@ radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, boo
 }
 
 nir_shader *
-radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, enum amd_gfx_level gfx_level,
-                                          uint32_t gb_addr_config, const struct radeon_surf *surf)
+radv_meta_nir_build_copy_vrs_htile_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
+                                          const struct radeon_surf *surf)
 {
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -967,12 +958,12 @@ radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, enum amd_g
 }
 
 nir_shader *
-radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, enum amd_gfx_level gfx_level,
-                                              uint32_t gb_addr_config, const struct radeon_surf *surf)
+radv_meta_nir_build_dcc_retile_compute_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
+                                              const struct radeon_surf *surf)
 {
    enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
    const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "dcc_retile_compute");
 
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
@@ -1017,11 +1008,11 @@ radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, enum amd_
 }
 
 nir_shader *
-radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev)
+radv_meta_nir_build_expand_depth_stencil_compute_shader()
 {
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
 
    /* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
    b.shader->info.workgroup_size[0] = 8;
@@ -1058,11 +1049,11 @@ radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev)
 }
 
 nir_shader *
-radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev)
+radv_meta_nir_build_dcc_decompress_compute_shader()
 {
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_decompress_compute");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "dcc_decompress_compute");
 
    /* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
    b.shader->info.workgroup_size[0] = 16;
@@ -1096,12 +1087,12 @@ radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev)
 }
 
 nir_shader *
-radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
+radv_meta_nir_build_fmask_copy_compute_shader(int samples)
 {
    const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
 
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
@@ -1157,12 +1148,12 @@ radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int sampl
 }
 
 nir_shader *
-radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int samples)
+radv_meta_nir_build_fmask_expand_compute_shader(int samples)
 {
    const struct glsl_type *type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, true, GLSL_TYPE_FLOAT);
 
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -1242,8 +1233,8 @@ get_resolve_mode_str(VkResolveModeFlagBits resolve_mode)
 }
 
 nir_shader *
-radv_meta_nir_build_resolve_cs(struct radv_device *dev, bool use_fmask, enum radv_meta_resolve_compute_type type,
-                               int samples, VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
+radv_meta_nir_build_resolve_cs(bool use_fmask, enum radv_meta_resolve_compute_type type, int samples,
+                               VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
 {
    enum glsl_base_type img_base_type =
       (aspects == VK_IMAGE_ASPECT_COLOR_BIT && type == RADV_META_RESOLVE_COMPUTE_INTEGER) ||
@@ -1253,7 +1244,7 @@ radv_meta_nir_build_resolve_cs(struct radv_device *dev, bool use_fmask, enum rad
    const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, img_base_type);
    const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, true, img_base_type);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_resolve_cs");
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -1297,8 +1288,8 @@ radv_meta_nir_build_resolve_cs(struct radv_device *dev, bool use_fmask, enum rad
 }
 
 nir_shader *
-radv_meta_nir_build_resolve_fs(struct radv_device *dev, bool use_fmask, int samples, bool is_integer,
-                               VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
+radv_meta_nir_build_resolve_fs(bool use_fmask, int samples, bool is_integer, VkImageAspectFlags aspects,
+                               VkResolveModeFlagBits resolve_mode)
 {
    enum glsl_base_type img_base_type =
       (aspects == VK_IMAGE_ASPECT_COLOR_BIT && is_integer) || aspects == VK_IMAGE_ASPECT_STENCIL_BIT ? GLSL_TYPE_UINT
@@ -1306,7 +1297,7 @@ radv_meta_nir_build_resolve_fs(struct radv_device *dev, bool use_fmask, int samp
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, img_base_type);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs");
 
    uint32_t location, writemask;
    switch (aspects) {
@@ -1351,11 +1342,11 @@ radv_meta_nir_build_resolve_fs(struct radv_device *dev, bool use_fmask, int samp
 }
 
 nir_shader *
-radv_meta_nir_build_clear_hiz_compute_shader(struct radv_device *dev, int samples)
+radv_meta_nir_build_clear_hiz_compute_shader(int samples)
 {
    const enum glsl_sampler_dim dim = samples > 1 ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
    const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_hiz_cs-%d", samples);
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_clear_hiz_cs-%d", samples);
    b.shader->info.workgroup_size[0] = 8;
    b.shader->info.workgroup_size[1] = 8;
 
@@ -1392,9 +1383,9 @@ nir_udiv_round_up(nir_builder *b, nir_def *n, nir_def *d)
 
 /* Copy memory->memory shaders. */
 nir_shader *
-radv_meta_nir_build_copy_memory_indirect_preprocess_cs(struct radv_device *dev)
+radv_meta_nir_build_copy_memory_indirect_preprocess_cs(void)
 {
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_copy_memory_indirect_preprocess_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_copy_memory_indirect_preprocess_cs");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *global_id = radv_meta_nir_get_global_ids(&b, 1);
@@ -1428,9 +1419,9 @@ radv_meta_nir_build_copy_memory_indirect_preprocess_cs(struct radv_device *dev)
 }
 
 nir_shader *
-radv_meta_nir_build_copy_memory_indirect_cs(struct radv_device *dev)
+radv_meta_nir_build_copy_memory_indirect_cs(void)
 {
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_copy_memory_indirect_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_copy_memory_indirect_cs");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *global_id = radv_meta_nir_get_global_ids(&b, 1);
@@ -1466,10 +1457,9 @@ radv_meta_nir_build_copy_memory_indirect_cs(struct radv_device *dev)
 
 /* Copy memory->image shaders. */
 nir_shader *
-radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(struct radv_device *dev)
+radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(void)
 {
-   nir_builder b =
-      radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_copy_memory_to_image_indirect_preprocess_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_copy_memory_to_image_indirect_preprocess_cs");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_def *global_id = radv_meta_nir_get_global_ids(&b, 1);
@@ -1560,13 +1550,11 @@ get_image_stride_B(nir_builder *b, nir_def *indirect_addr, nir_def *row_stride_B
 }
 
 nir_shader *
-radv_meta_nir_build_copy_memory_to_image_indirect_cs(struct radv_device *dev, uint8_t fmt_block_width,
-                                                     uint8_t fmt_block_height, uint8_t fmt_block_depth,
-                                                     uint8_t fmt_element_size_B, bool is_3d)
+radv_meta_nir_build_copy_memory_to_image_indirect_cs(uint8_t fmt_block_width, uint8_t fmt_block_height,
+                                                     uint8_t fmt_block_depth, uint8_t fmt_element_size_B, bool is_3d)
 {
-   nir_builder b = radv_meta_nir_init_shader(
-      dev, MESA_SHADER_COMPUTE,
-      is_3d ? "meta_copy_memory_to_image_indirect_3d_cs" : "meta_copy_memory_to_image_indirect_cs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_copy_memory_to_image_indirect_3d_cs"
+                                                                        : "meta_copy_memory_to_image_indirect_cs");
    b.shader->info.workgroup_size[0] = 64;
 
    enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
@@ -1634,12 +1622,12 @@ radv_meta_nir_build_copy_memory_to_image_indirect_cs(struct radv_device *dev, ui
 }
 
 nir_shader *
-radv_meta_nir_build_copy_memory_to_image_indirect_vs(struct radv_device *dev, uint8_t fmt_block_width,
-                                                     uint8_t fmt_block_height, uint8_t fmt_block_depth)
+radv_meta_nir_build_copy_memory_to_image_indirect_vs(uint8_t fmt_block_width, uint8_t fmt_block_height,
+                                                     uint8_t fmt_block_depth)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vec2_type();
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_copy_memory_to_image_indirect_vs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_VERTEX, "meta_copy_memory_to_image_indirect_vs");
 
    nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
    pos_out->data.location = VARYING_SLOT_POS;
@@ -1699,15 +1687,14 @@ radv_meta_nir_build_copy_memory_to_image_indirect_vs(struct radv_device *dev, ui
 }
 
 nir_shader *
-radv_meta_nir_build_copy_memory_to_image_indirect_fs(struct radv_device *dev, VkImageAspectFlags aspect_mask,
-                                                     uint8_t fmt_block_width, uint8_t fmt_block_height,
-                                                     uint8_t fmt_element_size_B)
+radv_meta_nir_build_copy_memory_to_image_indirect_fs(VkImageAspectFlags aspect_mask, uint8_t fmt_block_width,
+                                                     uint8_t fmt_block_height, uint8_t fmt_element_size_B)
 {
    const struct glsl_type *vec4 = glsl_vec4_type();
    const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
    uint32_t output_channels;
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_copy_memory_to_image_indirect_fs");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_FRAGMENT, "meta_copy_memory_to_image_indirect_fs");
 
    nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
    tex_pos_in->data.location = VARYING_SLOT_VAR0;
diff --git a/src/amd/vulkan/nir/radv_meta_nir.h b/src/amd/vulkan/nir/radv_meta_nir.h
index 5d4e1d08ce5..6d3372ad93f 100644
--- a/src/amd/vulkan/nir/radv_meta_nir.h
+++ b/src/amd/vulkan/nir/radv_meta_nir.h
@@ -18,34 +18,31 @@
 extern "C" {
 #endif
 
-struct radv_device;
 struct radeon_surf;
 enum amd_gfx_level;
 
-nir_builder PRINTFLIKE(3, 4)
-   radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...);
+nir_builder PRINTFLIKE(2, 3) radv_meta_nir_init_shader(mesa_shader_stage stage, const char *name, ...);
 
-nir_shader *radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev);
-nir_shader *radv_meta_nir_build_fs_noop(struct radv_device *dev);
+nir_shader *radv_meta_nir_build_vs_generate_vertices(void);
+nir_shader *radv_meta_nir_build_fs_noop(void);
 
 nir_def *radv_meta_nir_get_global_ids(nir_builder *b, unsigned num_components);
 
 void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
 
-nir_shader *radv_meta_nir_build_fill_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation);
-nir_shader *radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation);
+nir_shader *radv_meta_nir_build_fill_memory_shader(uint32_t bytes_per_invocation);
+nir_shader *radv_meta_nir_build_copy_memory_shader(uint32_t bytes_per_invocation);
 
-nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev);
-nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
-nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
-nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev,
-                                                                  enum glsl_sampler_dim tex_dim);
+nir_shader *radv_meta_nir_build_blit_vertex_shader(void);
+nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(enum glsl_sampler_dim tex_dim);
+nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim);
+nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim);
 
-nir_shader *radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d);
-nir_shader *radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d);
-nir_shader *radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bool dst_3d, int samples);
-nir_shader *radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples);
-nir_shader *radv_meta_nir_build_cleari_96bit_compute_shader(struct radv_device *dev);
+nir_shader *radv_meta_nir_build_itob_compute_shader(bool is_3d);
+nir_shader *radv_meta_nir_build_btoi_compute_shader(bool is_3d);
+nir_shader *radv_meta_nir_build_itoi_compute_shader(bool src_3d, bool dst_3d, int samples);
+nir_shader *radv_meta_nir_build_cleari_compute_shader(bool is_3d, int samples);
+nir_shader *radv_meta_nir_build_cleari_96bit_compute_shader(void);
 
 typedef nir_def *(*radv_meta_nir_texel_fetch_build_func)(nir_builder *, uint32_t, nir_def *, bool, bool);
 nir_def *radv_meta_nir_build_blit2d_texel_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
@@ -53,41 +50,37 @@ nir_def *radv_meta_nir_build_blit2d_texel_fetch(nir_builder *b, uint32_t binding
 nir_def *radv_meta_nir_build_blit2d_buffer_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
                                                  bool is_multisampled);
 
-nir_shader *radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device);
-nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
-                                                            radv_meta_nir_texel_fetch_build_func txf_func,
+nir_shader *radv_meta_nir_build_blit2d_vertex_shader(void);
+nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(radv_meta_nir_texel_fetch_build_func txf_func,
                                                             const char *name, bool is_3d, bool is_multisampled);
-nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device,
-                                                                  radv_meta_nir_texel_fetch_build_func txf_func,
+nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(radv_meta_nir_texel_fetch_build_func txf_func,
                                                                   const char *name, bool is_3d, bool is_multisampled);
-nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *device,
-                                                                    radv_meta_nir_texel_fetch_build_func txf_func,
+nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(radv_meta_nir_texel_fetch_build_func txf_func,
                                                                     const char *name, bool is_3d, bool is_multisampled);
-nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(struct radv_device *device,
-                                                                          radv_meta_nir_texel_fetch_build_func txf_func,
+nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(radv_meta_nir_texel_fetch_build_func txf_func,
                                                                           const char *name, bool is_3d,
                                                                           bool is_multisampled);
 
-void radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs,
-                                             struct nir_shader **out_fs, uint32_t frag_output);
-void radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
-                                                    struct nir_shader **out_fs, bool unrestricted);
-nir_shader *radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev);
-nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa);
+void radv_meta_nir_build_clear_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs,
+                                             uint32_t frag_output);
+void radv_meta_nir_build_clear_depthstencil_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs,
+                                                    bool unrestricted);
+nir_shader *radv_meta_nir_build_clear_htile_mask_shader(void);
+nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(bool is_msaa);
 
-nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, enum amd_gfx_level gfx_level,
-                                                      uint32_t gb_addr_config, const struct radeon_surf *surf);
+nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
+                                                      const struct radeon_surf *surf);
 
-nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, enum amd_gfx_level gfx_level,
-                                                          uint32_t gb_addr_config, const struct radeon_surf *surf);
+nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
+                                                          const struct radeon_surf *surf);
 
-nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev);
+nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(void);
 
-nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev);
+nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(void);
 
-nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int samples);
+nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(int samples);
 
-nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int samples);
+nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(int samples);
 
 enum radv_meta_resolve_compute_type {
    RADV_META_RESOLVE_COMPUTE_NORM,
@@ -97,26 +90,24 @@ enum radv_meta_resolve_compute_type {
    RADV_META_RESOLVE_COMPUTE_COUNT,
 };
 
-nir_shader *radv_meta_nir_build_resolve_cs(struct radv_device *dev, bool use_fmask,
-                                           enum radv_meta_resolve_compute_type type, int samples,
-                                           VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode);
-nir_shader *radv_meta_nir_build_resolve_fs(struct radv_device *dev, bool use_fmask, int samples, bool is_integer,
+nir_shader *radv_meta_nir_build_resolve_cs(bool use_fmask, enum radv_meta_resolve_compute_type type, int samples,
                                            VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode);
+nir_shader *radv_meta_nir_build_resolve_fs(bool use_fmask, int samples, bool is_integer, VkImageAspectFlags aspects,
+                                           VkResolveModeFlagBits resolve_mode);
 
-nir_shader *radv_meta_nir_build_clear_hiz_compute_shader(struct radv_device *dev, int samples);
+nir_shader *radv_meta_nir_build_clear_hiz_compute_shader(int samples);
 
-nir_shader *radv_meta_nir_build_copy_memory_indirect_preprocess_cs(struct radv_device *dev);
-nir_shader *radv_meta_nir_build_copy_memory_indirect_cs(struct radv_device *dev);
+nir_shader *radv_meta_nir_build_copy_memory_indirect_preprocess_cs(void);
+nir_shader *radv_meta_nir_build_copy_memory_indirect_cs(void);
 
-nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(struct radv_device *dev);
-nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_cs(struct radv_device *dev, uint8_t fmt_block_width,
-                                                                 uint8_t fmt_block_height, uint8_t fmt_block_depth,
-                                                                 uint8_t fmt_element_size_B, bool is_3d);
+nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(void);
+nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_cs(uint8_t fmt_block_width, uint8_t fmt_block_height,
+                                                                 uint8_t fmt_block_depth, uint8_t fmt_element_size_B,
+                                                                 bool is_3d);
 
-nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_vs(struct radv_device *dev, uint8_t fmt_block_width,
-                                                                 uint8_t fmt_block_height, uint8_t fmt_block_depth);
-nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_fs(struct radv_device *dev,
-                                                                 VkImageAspectFlags aspect_mask,
+nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_vs(uint8_t fmt_block_width, uint8_t fmt_block_height,
+                                                                 uint8_t fmt_block_depth);
+nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_fs(VkImageAspectFlags aspect_mask,
                                                                  uint8_t fmt_block_width, uint8_t fmt_block_height,
                                                                  uint8_t fmt_element_size_B);
 
diff --git a/src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c b/src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
index cd4030069b4..3ba8aeffab6 100644
--- a/src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
+++ b/src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
@@ -1296,7 +1296,7 @@ radv_build_traversal_shader(struct radv_device *device, struct radv_ray_tracing_
 
    /* Create the traversal shader as an intersection shader to prevent validation failures due to
     * invalid variable modes.*/
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_INTERSECTION, "rt_traversal");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_INTERSECTION, "rt_traversal");
    b.shader->options = &pdev->nir_options[MESA_SHADER_INTERSECTION];
    b.shader->info.workgroup_size[0] = pdev->rt_wave_size;
    b.shader->info.api_subgroup_size = pdev->rt_wave_size;
diff --git a/src/amd/vulkan/radv_dgc.c b/src/amd/vulkan/radv_dgc.c
index 690f606c25b..f01f104c20e 100644
--- a/src/amd/vulkan/radv_dgc.c
+++ b/src/amd/vulkan/radv_dgc.c
@@ -2884,7 +2884,7 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l
 {
    const struct radv_physical_device *pdev = radv_device_physical(dev);
 
-   nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_dgc_prepare");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "meta_dgc_prepare");
    b.shader->info.workgroup_size[0] = 64;
 
    struct dgc_cmdbuf cmd_buf = {
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 8c02d060c45..e26a8bd0762 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -158,8 +158,7 @@ radv_occlusion_query_use_l2(const struct radv_physical_device *pdev)
 }
 
 static nir_shader *
-build_occlusion_query_shader(struct radv_device *device, uint64_t enabled_rb_mask, uint32_t max_render_backends,
-                             bool use_l2)
+build_occlusion_query_shader(uint64_t enabled_rb_mask, uint32_t max_render_backends, bool use_l2)
 {
    /* the shader this builds is roughly
     *
@@ -200,7 +199,7 @@ build_occlusion_query_shader(struct radv_device *device, uint64_t enabled_rb_mas
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "occlusion_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "occlusion_query");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
@@ -416,8 +415,7 @@ radv_get_pipelinestat_query_size(struct radv_device *device)
 }
 
 static nir_shader *
-build_pipeline_statistics_query_shader(struct radv_device *device, uint32_t pipelinestat_block_size,
-                                       bool emulate_mesh_shader_queries)
+build_pipeline_statistics_query_shader(uint32_t pipelinestat_block_size, bool emulate_mesh_shader_queries)
 {
    /* the shader this builds is roughly
     *
@@ -461,7 +459,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device, uint32_t pipe
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "pipeline_statistics_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "pipeline_statistics_query");
    b.shader->info.workgroup_size[0] = 64;
 
    nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
@@ -808,7 +806,7 @@ radv_copy_pipeline_stat_query_result(struct radv_cmd_buffer *cmd_buffer, struct
  * Transform feedback query
  */
 static nir_shader *
-build_tfb_query_shader(struct radv_device *device)
+build_tfb_query_shader()
 {
    /* the shader this builds is roughly
     *
@@ -845,7 +843,7 @@ build_tfb_query_shader(struct radv_device *device)
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "tfb_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "tfb_query");
    b.shader->info.workgroup_size[0] = 64;
 
    /* Create and initialize local variables. */
@@ -1050,7 +1048,7 @@ radv_copy_tfb_query_result(struct radv_cmd_buffer *cmd_buffer, struct radv_query
  * Timestamp query
  */
 static nir_shader *
-build_timestamp_query_shader(struct radv_device *device)
+build_timestamp_query_shader()
 {
    /* the shader this builds is roughly
     *
@@ -1082,7 +1080,7 @@ build_timestamp_query_shader(struct radv_device *device)
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "timestamp_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "timestamp_query");
    b.shader->info.workgroup_size[0] = 64;
 
    /* Create and initialize local variables. */
@@ -1185,7 +1183,7 @@ radv_copy_timestamp_query_result(struct radv_cmd_buffer *cmd_buffer, struct radv
 #define RADV_PGQ_STRIDE_EMU (RADV_PGQ_STRIDE + 8 * 2)
 
 static nir_shader *
-build_pg_query_shader(struct radv_device *device)
+build_pg_query_shader()
 {
    /* the shader this builds is roughly
     *
@@ -1224,7 +1222,7 @@ build_pg_query_shader(struct radv_device *device)
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "pg_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "pg_query");
    b.shader->info.workgroup_size[0] = 64;
 
    /* Create and initialize local variables. */
@@ -1464,7 +1462,7 @@ radv_copy_pg_query_result(struct radv_cmd_buffer *cmd_buffer, struct radv_query_
  * Mesh primitives generated query
  */
 static nir_shader *
-build_ms_prim_gen_query_shader(struct radv_device *device)
+build_ms_prim_gen_query_shader()
 {
    /* the shader this builds is roughly
     *
@@ -1497,7 +1495,7 @@ build_ms_prim_gen_query_shader(struct radv_device *device)
     * 	}
     * }
     */
-   nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "ms_prim_gen_query");
+   nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_COMPUTE, "ms_prim_gen_query");
    b.shader->info.workgroup_size[0] = 64;
 
    /* Create and initialize local variables. */
@@ -1740,24 +1738,24 @@ get_pipeline(struct radv_device *device, VkQueryType query_type, VkPipeline *pip
 
    switch (query_type) {
    case VK_QUERY_TYPE_OCCLUSION:
-      cs = build_occlusion_query_shader(device, pdev->info.enabled_rb_mask, pdev->info.max_render_backends,
+      cs = build_occlusion_query_shader(pdev->info.enabled_rb_mask, pdev->info.max_render_backends,
                                         radv_occlusion_query_use_l2(pdev));
       break;
    case VK_QUERY_TYPE_PIPELINE_STATISTICS:
-      cs = build_pipeline_statistics_query_shader(device, radv_get_pipelinestat_query_size(device),
+      cs = build_pipeline_statistics_query_shader(radv_get_pipelinestat_query_size(device),
                                                   pdev->emulate_mesh_shader_queries);
       break;
    case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
-      cs = build_tfb_query_shader(device);
+      cs = build_tfb_query_shader();
       break;
    case VK_QUERY_TYPE_TIMESTAMP:
-      cs = build_timestamp_query_shader(device);
+      cs = build_timestamp_query_shader();
       break;
    case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT:
-      cs = build_pg_query_shader(device);
+      cs = build_pg_query_shader();
       break;
    case VK_QUERY_TYPE_MESH_PRIMITIVES_GENERATED_EXT:
-      cs = build_ms_prim_gen_query_shader(device);
+      cs = build_ms_prim_gen_query_shader();
       break;
    default:
       UNREACHABLE("invalid query type");
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index cecbf4c2af3..243f1e33f52 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -3381,7 +3381,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
    radv_fill_nir_compiler_options(&options, device, NULL, radv_should_use_wgp_mode(pdev->info.gfx_level, stage, &info),
                                   dump_shader, false, false);
 
-   nir_builder b = radv_meta_nir_init_shader(device, stage, "meta_trap_handler");
+   nir_builder b = radv_meta_nir_init_shader(stage, "meta_trap_handler");
 
    info.wave_size = 64;
    info.workgroup_size = 64;