From 12d7aaf2b825fe49277b84a605733e8fc39e241d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Wed, 8 Mar 2023 13:21:48 +0200
Subject: [PATCH] intel/compiler: add more validation for acc register usage
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This is described in Wa_14014617373 and a programming note has
been added to specification.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23682>
---
 src/intel/compiler/brw_fs_validate.cpp | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/intel/compiler/brw_fs_validate.cpp b/src/intel/compiler/brw_fs_validate.cpp
index f6e18d48a05..98d149e224b 100644
--- a/src/intel/compiler/brw_fs_validate.cpp
+++ b/src/intel/compiler/brw_fs_validate.cpp
@@ -192,6 +192,17 @@ fs_visitor::validate()
                            alloc.sizes[inst->src[i].nr]);
          }
       }
+
+      /* Accumulator Registers, bspec 47251:
+       *
+       * "When destination is accumulator with offset 0, destination
+       * horizontal stride must be 1."
+       */
+      if (intel_needs_workaround(devinfo, 14014617373) &&
+          inst->dst.is_accumulator() &&
+          inst->dst.offset == 0) {
+         fsv_assert_eq(inst->dst.stride, 1);
+      }
    }
 #endif
 }