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intel/compiler: Add instruction compaction support on Gen12

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Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Matt Turner 2019-09-09 13:01:06 -07:00
parent c8fbc8823f
commit 12d3b11908
2 changed files with 867 additions and 183 deletions
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1038
src/intel/compiler/brw_eu_compact.c
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File diff suppressed because it is too large Load diff

12
src/intel/compiler/brw_inst.h
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@ -1397,6 +1397,18 @@ FC(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->gen >= 12)
F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7) F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7)
F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */ F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
static inline unsigned
brw_compact_inst_imm(const struct gen_device_info *devinfo,
const brw_compact_inst *inst)
{
if (devinfo->gen >= 12) {
return brw_compact_inst_bits(inst, 63, 52);
} else {
return (brw_compact_inst_bits(inst, 39, 35) << 8) |
(brw_compact_inst_bits(inst, 63, 56));
}
}
/** /**
* (Gen8+) Compacted three-source instructions: * (Gen8+) Compacted three-source instructions:
* @{ * @{