gallium/radeon: send the END_OF_FRAME flag to the DRM

This commit is contained in:
Marek Olšák 2012-12-21 17:15:56 +01:00
parent 598cc1f74d
commit 12aeb47b6a
5 changed files with 16 additions and 5 deletions

View file

@ -136,7 +136,9 @@ static void r300_flush_wrapped(struct pipe_context *pipe,
struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
r300_flush(pipe, 0, fence);
r300_flush(pipe,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0,
fence);
}
void r300_init_flush_functions(struct r300_context* r300)

View file

@ -146,7 +146,8 @@ static void r600_flush_from_st(struct pipe_context *ctx,
struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
r600_flush(ctx, fence, 0);
r600_flush(ctx, fence,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)

View file

@ -161,7 +161,8 @@ static void r600_flush_from_st(struct pipe_context *ctx,
struct pipe_fence_handle **fence,
enum pipe_flush_flags flags)
{
radeonsi_flush(ctx, fence, 0);
radeonsi_flush(ctx, fence,
flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)

View file

@ -81,8 +81,6 @@
/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
#define RADEON_CS_KEEP_TILING_FLAGS 0x01
#endif
#ifndef RADEON_CS_USE_VM
@ -92,6 +90,10 @@
#define RADEON_CS_RING_COMPUTE 1
#endif
#ifndef RADEON_CS_END_OF_FRAME
#define RADEON_CS_END_OF_FRAME 0x04
#endif
#define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
@ -473,6 +475,10 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags)
cs->cst->flags[0] |= RADEON_CS_USE_VM;
cs->cst->cs.num_chunks = 3;
}
if (flags & RADEON_FLUSH_END_OF_FRAME) {
cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
cs->cst->cs.num_chunks = 3;
}
if (flags & RADEON_FLUSH_COMPUTE) {
cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
cs->cst->cs.num_chunks = 3;

View file

@ -48,6 +48,7 @@
#define RADEON_FLUSH_ASYNC (1 << 0)
#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
#define RADEON_FLUSH_COMPUTE (1 << 2)
#define RADEON_FLUSH_END_OF_FRAME (1 << 3)
/* Tiling flags. */
enum radeon_bo_layout {