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radeon/llvm: use IntrNoMem property for intrinsics where possible
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Vadim Girlin
parent
63a8595271
commit
12a2374da3
7 changed files with 171 additions and 105 deletions
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@ -21,10 +21,11 @@ static LLVMValueRef llvm_fetch_const(
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enum tgsi_opcode_type type,
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unsigned swizzle)
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{
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LLVMValueRef cval = lp_build_intrinsic_unary(bld_base->base.gallivm->builder,
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LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
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radeon_llvm_reg_index_soa(reg->Register.Index, swizzle));
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LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
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"llvm.AMDGPU.load.const", bld_base->base.elem_type,
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lp_build_const_int32(bld_base->base.gallivm,
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radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)));
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&idx, 1, LLVMReadNoneAttribute);
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return bitcast(bld_base, type, cval);
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}
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@ -44,10 +45,11 @@ static void llvm_load_system_value(
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LLVMValueRef reg = lp_build_const_int32(
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ctx->soa.bld_base.base.gallivm, chan);
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ctx->system_values[index] = lp_build_intrinsic_unary(
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ctx->system_values[index] = build_intrinsic(
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ctx->soa.bld_base.base.gallivm->builder,
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"llvm.R600.load.input",
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ctx->soa.bld_base.base.elem_type, reg);
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ctx->soa.bld_base.base.elem_type, ®, 1,
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LLVMReadNoneAttribute);
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}
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static LLVMValueRef llvm_fetch_system_value(
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@ -76,10 +78,11 @@ static void llvm_load_input(
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LLVMValueRef reg = lp_build_const_int32(
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ctx->soa.bld_base.base.gallivm,
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soa_index + (ctx->reserved_reg_count * 4));
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ctx->inputs[soa_index] = lp_build_intrinsic_unary(
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ctx->inputs[soa_index] = build_intrinsic(
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ctx->soa.bld_base.base.gallivm->builder,
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"llvm.R600.load.input",
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ctx->soa.bld_base.base.elem_type, reg);
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ctx->soa.bld_base.base.elem_type, ®, 1,
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LLVMReadNoneAttribute);
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}
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}
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@ -146,9 +149,9 @@ static void llvm_emit_tex(
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emit_data->inst->Src[1].Register.Index);
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args[2] = lp_build_const_int32(gallivm,
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emit_data->inst->Texture.Texture);
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emit_data->output[0] = lp_build_intrinsic(gallivm->builder,
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emit_data->output[0] = build_intrinsic(gallivm->builder,
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action->intr_name,
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emit_data->dst_type, args, 3);
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emit_data->dst_type, args, 3, LLVMReadNoneAttribute);
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}
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static void dp_fetch_args(
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@ -189,7 +192,7 @@ static void dp_fetch_args(
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static struct lp_build_tgsi_action dot_action = {
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.fetch_args = dp_fetch_args,
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.emit = lp_build_tgsi_intrinsic,
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.emit = build_tgsi_intrinsic_nomem,
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.intr_name = "llvm.AMDGPU.dp4"
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};
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@ -13,47 +13,47 @@
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let TargetPrefix = "AMDGPU", isTarget = 1 in {
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def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>;
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def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], []>;
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def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], []>;
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def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
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def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], []>;
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def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_cos : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
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def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_cos : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
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def int_AMDGPU_kilp : Intrinsic<[], [], []>;
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def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_pow : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_rcp : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_sin : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_ssg : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
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def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>;
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def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_pow : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_rcp : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_sin : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_ssg : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
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def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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}
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let TargetPrefix = "TGSI", isTarget = 1 in {
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@ -407,34 +407,34 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
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class VoidIntBool :
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Intrinsic<[llvm_i32_ty], [], []>;
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class UnaryIntInt :
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], []>;
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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class UnaryIntFloat :
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], []>;
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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class ConvertIntFTOI :
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Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], []>;
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Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
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class ConvertIntITOF :
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Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], []>;
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Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], [IntrNoMem]>;
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class UnaryIntNoRetInt :
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Intrinsic<[], [llvm_anyint_ty], []>;
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class UnaryIntNoRetFloat :
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Intrinsic<[], [llvm_anyfloat_ty], []>;
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class BinaryIntInt :
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], []>;
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class BinaryIntFloat :
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], []>;
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class BinaryIntNoRetInt :
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Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>;
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class BinaryIntNoRetFloat :
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Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>;
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class TernaryIntInt :
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>], []>;
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LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class TernaryIntFloat :
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>], []>;
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LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class QuaternaryIntInt :
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], []>;
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LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class UnaryAtomicInt :
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
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class BinaryAtomicInt :
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "R600", isTarget = 1 in {
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def int_R600_load_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadWriteArgMem]>;
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def int_R600_load_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
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}
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let TargetPrefix = "r600", isTarget = 1 in {
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@ -12,5 +12,5 @@
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "R600", isTarget = 1 in {
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def int_R600_load_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadWriteArgMem]>;
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def int_R600_load_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
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}
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@ -157,4 +157,20 @@ unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
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void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
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LLVMValueRef
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build_intrinsic(LLVMBuilderRef builder,
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const char *name,
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LLVMTypeRef ret_type,
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LLVMValueRef *args,
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unsigned num_args,
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LLVMAttribute attr);
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void
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build_tgsi_intrinsic_nomem(
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const struct lp_build_tgsi_action * action,
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data);
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#endif /* RADEON_LLVM_H */
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@ -34,8 +34,10 @@
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#include "tgsi/tgsi_info.h"
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#include "tgsi/tgsi_parse.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "util/u_debug.h"
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#include <llvm-c/Core.h>
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#include <llvm-c/Transforms/Scalar.h>
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static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
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@ -522,9 +524,9 @@ static void emit_prepare_cube_coords(
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LLVMValueRef mad_args[3];
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unsigned i, cnt;
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LLVMValueRef v = lp_build_intrinsic(builder, "llvm.AMDGPU.cube",
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LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
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LLVMVectorType(type, 4),
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&emit_data->args[0],1);
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&emit_data->args[0],1, LLVMReadNoneAttribute);
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/* save src.w for shadow cube */
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cnt = shadowcube ? 3 : 4;
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@ -534,21 +536,21 @@ static void emit_prepare_cube_coords(
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coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
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}
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coords[2] = lp_build_intrinsic(builder, "llvm.AMDIL.fabs.",
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type, &coords[2], 1);
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coords[2] = lp_build_intrinsic(builder, "llvm.AMDGPU.rcp",
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type, &coords[2], 1);
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coords[2] = build_intrinsic(builder, "llvm.AMDIL.fabs.",
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type, &coords[2], 1, LLVMReadNoneAttribute);
|
||||
coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp",
|
||||
type, &coords[2], 1, LLVMReadNoneAttribute);
|
||||
|
||||
mad_args[1] = coords[2];
|
||||
mad_args[2] = LLVMConstReal(type, 1.5);
|
||||
|
||||
mad_args[0] = coords[0];
|
||||
coords[0] = lp_build_intrinsic(builder, "llvm.AMDIL.mad.",
|
||||
type, mad_args, 3);
|
||||
coords[0] = build_intrinsic(builder, "llvm.AMDIL.mad.",
|
||||
type, mad_args, 3, LLVMReadNoneAttribute);
|
||||
|
||||
mad_args[0] = coords[1];
|
||||
coords[1] = lp_build_intrinsic(builder, "llvm.AMDIL.mad.",
|
||||
type, mad_args, 3);
|
||||
coords[1] = build_intrinsic(builder, "llvm.AMDIL.mad.",
|
||||
type, mad_args, 3, LLVMReadNoneAttribute);
|
||||
|
||||
/* apply yxwy swizzle to cooords */
|
||||
coords[2] = coords[3];
|
||||
|
|
@ -859,6 +861,51 @@ static void emit_immediate(struct lp_build_tgsi_context * bld_base,
|
|||
ctx->soa.num_immediates++;
|
||||
}
|
||||
|
||||
LLVMValueRef
|
||||
build_intrinsic(LLVMBuilderRef builder,
|
||||
const char *name,
|
||||
LLVMTypeRef ret_type,
|
||||
LLVMValueRef *args,
|
||||
unsigned num_args,
|
||||
LLVMAttribute attr)
|
||||
{
|
||||
LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
|
||||
LLVMValueRef function;
|
||||
|
||||
function = LLVMGetNamedFunction(module, name);
|
||||
if(!function) {
|
||||
LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
|
||||
unsigned i;
|
||||
|
||||
assert(num_args <= LP_MAX_FUNC_ARGS);
|
||||
|
||||
for(i = 0; i < num_args; ++i) {
|
||||
assert(args[i]);
|
||||
arg_types[i] = LLVMTypeOf(args[i]);
|
||||
}
|
||||
|
||||
function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
|
||||
|
||||
if (attr)
|
||||
LLVMAddFunctionAttr(function, attr);
|
||||
}
|
||||
|
||||
return LLVMBuildCall(builder, function, args, num_args, "");
|
||||
}
|
||||
|
||||
void
|
||||
build_tgsi_intrinsic_nomem(
|
||||
const struct lp_build_tgsi_action * action,
|
||||
struct lp_build_tgsi_context * bld_base,
|
||||
struct lp_build_emit_data * emit_data)
|
||||
{
|
||||
struct lp_build_context * base = &bld_base->base;
|
||||
emit_data->output[emit_data->chan] = build_intrinsic(
|
||||
base->gallivm->builder, action->intr_name,
|
||||
emit_data->dst_type, emit_data->args,
|
||||
emit_data->arg_count, LLVMReadNoneAttribute);
|
||||
}
|
||||
|
||||
void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
|
||||
{
|
||||
struct lp_type type;
|
||||
|
|
@ -918,7 +965,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
|
|||
|
||||
lp_set_default_actions(bld_base);
|
||||
|
||||
bld_base->op_actions[TGSI_OPCODE_IABS].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
|
||||
bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
|
||||
bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
|
||||
|
|
@ -949,91 +996,91 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
|
|||
bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
|
||||
bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
|
||||
bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
|
||||
bld_base->op_actions[TGSI_OPCODE_ROUND].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
|
||||
bld_base->op_actions[TGSI_OPCODE_IMIN].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
|
||||
bld_base->op_actions[TGSI_OPCODE_IMAX].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
|
||||
bld_base->op_actions[TGSI_OPCODE_UMIN].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
|
||||
bld_base->op_actions[TGSI_OPCODE_UMAX].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
|
||||
bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = tex_fetch_args;
|
||||
bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
|
||||
bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
|
||||
bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
|
||||
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf.";
|
||||
|
||||
|
||||
|
||||
bld_base->op_actions[TGSI_OPCODE_ABS].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.AMDIL.fabs.";
|
||||
bld_base->op_actions[TGSI_OPCODE_ARL].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
|
||||
bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
|
||||
bld_base->op_actions[TGSI_OPCODE_CMP].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
|
||||
bld_base->op_actions[TGSI_OPCODE_COS].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos";
|
||||
bld_base->op_actions[TGSI_OPCODE_DIV].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
|
||||
bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_EX2].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
|
||||
bld_base->op_actions[TGSI_OPCODE_FLR].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor";
|
||||
bld_base->op_actions[TGSI_OPCODE_FRC].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
|
||||
bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
|
||||
bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
|
||||
bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
|
||||
bld_base->op_actions[TGSI_OPCODE_LG2].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log.";
|
||||
bld_base->op_actions[TGSI_OPCODE_LRP].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
|
||||
bld_base->op_actions[TGSI_OPCODE_MAD].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
|
||||
bld_base->op_actions[TGSI_OPCODE_MUL].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
|
||||
bld_base->op_actions[TGSI_OPCODE_POW].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.AMDGPU.pow";
|
||||
bld_base->op_actions[TGSI_OPCODE_RCP].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
|
||||
bld_base->op_actions[TGSI_OPCODE_SSG].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg";
|
||||
bld_base->op_actions[TGSI_OPCODE_SGE].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SGE].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SGE].intr_name = "llvm.AMDGPU.sge";
|
||||
bld_base->op_actions[TGSI_OPCODE_SEQ].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SEQ].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SEQ].intr_name = "llvm.AMDGPU.seq";
|
||||
bld_base->op_actions[TGSI_OPCODE_SLE].fetch_args = radeon_llvm_fetch_args_2_reverse_soa;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLE].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLE].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLE].intr_name = "llvm.AMDGPU.sge";
|
||||
bld_base->op_actions[TGSI_OPCODE_SLT].fetch_args = radeon_llvm_fetch_args_2_reverse_soa;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLT].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLT].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SLT].intr_name = "llvm.AMDGPU.sgt";
|
||||
bld_base->op_actions[TGSI_OPCODE_SNE].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SNE].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SNE].intr_name = "llvm.AMDGPU.sne";
|
||||
bld_base->op_actions[TGSI_OPCODE_SGT].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SGT].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SGT].intr_name = "llvm.AMDGPU.sgt";
|
||||
bld_base->op_actions[TGSI_OPCODE_SIN].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.AMDGPU.sin";
|
||||
bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
|
||||
bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
|
||||
|
|
@ -1045,10 +1092,10 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
|
|||
bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
|
||||
bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
|
||||
bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
|
||||
bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
|
||||
|
||||
bld_base->rsq_action.emit = lp_build_tgsi_intrinsic;
|
||||
bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
|
||||
bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue