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tu: Correctly set GRAS_LRZ_CB_CNTL

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590>
This commit is contained in:
Connor Abbott 2025-05-19 20:02:47 -04:00 • committed by Marge Bot
parent 50aa66a7c1
commit 12779451ee
3 changed files with 9 additions and 5 deletions
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4
src/freedreno/fdl/freedreno_lrz_layout.h
View file

@ -17,6 +17,7 @@ struct fdl_lrz_layout {
uint32_t lrz_pitch;
uint32_t lrz_height;
uint32_t lrz_layer_size;
uint32_t lrz_buffer_size;
uint32_t lrz_fc_offset;
uint32_t lrz_fc_size;
uint32_t lrz_total_size;
@ -63,6 +64,7 @@ fdl6_lrz_layout_init(struct fdl_lrz_layout *lrz_layout,
lrz_layout->lrz_height = lrz_height;
lrz_layout->lrz_pitch = lrz_pitch;
lrz_layout->lrz_layer_size = lrz_pitch * lrz_height * sizeof(uint16_t);
lrz_layout->lrz_buffer_size = lrz_layout->lrz_layer_size * array_layers;
unsigned nblocksx = DIV_ROUND_UP(DIV_ROUND_UP(width, 8), 16);
unsigned nblocksy = DIV_ROUND_UP(DIV_ROUND_UP(height, 8), 4);
@ -78,7 +80,7 @@ fdl6_lrz_layout_init(struct fdl_lrz_layout *lrz_layout,
lrz_layout->lrz_fc_size = 0;
}
uint32_t lrz_size = lrz_layout->lrz_layer_size * array_layers;
uint32_t lrz_size = lrz_layout->lrz_buffer_size;
if (dev_info->a6xx.enable_lrz_fast_clear ||
dev_info->a6xx.has_lrz_dir_tracking) {
lrz_layout->lrz_fc_offset =

4
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1984,7 +1984,7 @@ tu7_emit_tile_render_begin_regs(struct tu_cs *cs)
tu_cs_emit_regs(cs,
A7XX_RB_CCU_DBG_ECO_CNTL(0x0));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL(0x0));
tu_cs_emit_regs(cs, GRAS_LRZ_CB_CNTL(A7XX, 0x0));
tu_cs_emit_regs(cs, GRAS_MODE_CNTL(A7XX, 0x2));
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
@ -2707,8 +2707,6 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit_regs(cs,
A7XX_RB_CCU_DBG_ECO_CNTL(cmd->device->physical_device->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL(0x0));
tu_cs_emit_regs(cs, GRAS_MODE_CNTL(A7XX, 0x2));
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));

6
src/freedreno/vulkan/tu_lrz.cc
View file

@ -115,8 +115,10 @@ tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image)
A6XX_GRAS_LRZ_BUFFER_PITCH(0),
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
if (CHIP >= A7XX)
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO());
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL());
}
return;
}
@ -138,6 +140,8 @@ tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image)
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO(
.depth_format = tu6_pipe2depth(depth_image->vk.format)
));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL(
.double_buffer_stride = depth_image->lrz_layout.lrz_buffer_size));
}
}