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st/nine: Fix alpha to coverage states

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The sequence of states to disable NVidia alpha
to coverage was disabling AMD alpha to coverage.
This patch fixes it.

Found with wine tests.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10160>
This commit is contained in:
Axel Davy 2021-03-11 20:43:04 +01:00 • committed by Marge Bot
parent d03f401fda
commit 1272640d55
2 changed files with 15 additions and 6 deletions
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2
src/gallium/frontends/nine/nine_pipe.c
View file

@ -166,7 +166,7 @@ nine_convert_blend_state(struct pipe_blend_state *blend_state, const DWORD *rs)
blend.dither = !!rs[D3DRS_DITHERENABLE]; blend.dither = !!rs[D3DRS_DITHERENABLE];
/* blend.alpha_to_one = 0; */ /* blend.alpha_to_one = 0; */
blend.alpha_to_coverage = rs[NINED3DRS_ALPHACOVERAGE] & 1; blend.alpha_to_coverage = !!(rs[NINED3DRS_ALPHACOVERAGE] & 5);
blend.rt[0].blend_enable = !!rs[D3DRS_ALPHABLENDENABLE]; blend.rt[0].blend_enable = !!rs[D3DRS_ALPHABLENDENABLE];
if (blend.rt[0].blend_enable) { if (blend.rt[0].blend_enable) {

19
src/gallium/frontends/nine/nine_state.c
View file

@ -1415,9 +1415,16 @@ CSMT_ITEM_NO_WAIT(nine_context_set_render_state,
return; return;
} }
/* NINED3DRS_ALPHACOVERAGE:
* bit 0: NVIDIA alpha to coverage
* bit 1: NVIDIA ATOC state active
* bit 2: AMD alpha to coverage
* These need to be separate else the set of states to
* disable NVIDIA alpha to coverage can disable the AMD one */
if (Value == ALPHA_TO_COVERAGE_ENABLE || if (Value == ALPHA_TO_COVERAGE_ENABLE ||
Value == ALPHA_TO_COVERAGE_DISABLE) { Value == ALPHA_TO_COVERAGE_DISABLE) {
context->rs[NINED3DRS_ALPHACOVERAGE] = (Value == ALPHA_TO_COVERAGE_ENABLE); context->rs[NINED3DRS_ALPHACOVERAGE] &= 3;
context->rs[NINED3DRS_ALPHACOVERAGE] |= (Value == ALPHA_TO_COVERAGE_ENABLE) ? 4 : 0;
context->changed.group |= NINE_STATE_BLEND; context->changed.group |= NINE_STATE_BLEND;
return; return;
} }
@ -1425,16 +1432,18 @@ CSMT_ITEM_NO_WAIT(nine_context_set_render_state,
/* NV hack */ /* NV hack */
if (unlikely(State == D3DRS_ADAPTIVETESS_Y)) { if (unlikely(State == D3DRS_ADAPTIVETESS_Y)) {
if (Value == D3DFMT_ATOC || (Value == D3DFMT_UNKNOWN && context->rs[NINED3DRS_ALPHACOVERAGE])) { if (Value == D3DFMT_ATOC || (Value == D3DFMT_UNKNOWN && context->rs[NINED3DRS_ALPHACOVERAGE] & 3)) {
context->rs[NINED3DRS_ALPHACOVERAGE] = (Value == D3DFMT_ATOC) ? 3 : 0; context->rs[NINED3DRS_ALPHACOVERAGE] &= 4;
context->rs[NINED3DRS_ALPHACOVERAGE] &= context->rs[D3DRS_ALPHATESTENABLE] ? 3 : 2; context->rs[NINED3DRS_ALPHACOVERAGE] |=
((Value == D3DFMT_ATOC) ? 3 : 0) & (context->rs[D3DRS_ALPHATESTENABLE] ? 3 : 2);
context->changed.group |= NINE_STATE_BLEND; context->changed.group |= NINE_STATE_BLEND;
return; return;
} }
} }
if (unlikely(State == D3DRS_ALPHATESTENABLE && (context->rs[NINED3DRS_ALPHACOVERAGE] & 2))) { if (unlikely(State == D3DRS_ALPHATESTENABLE && (context->rs[NINED3DRS_ALPHACOVERAGE] & 2))) {
DWORD alphacoverage_prev = context->rs[NINED3DRS_ALPHACOVERAGE]; DWORD alphacoverage_prev = context->rs[NINED3DRS_ALPHACOVERAGE];
context->rs[NINED3DRS_ALPHACOVERAGE] = (Value ? 3 : 2); context->rs[NINED3DRS_ALPHACOVERAGE] &= 6;
context->rs[NINED3DRS_ALPHACOVERAGE] |= (context->rs[D3DRS_ALPHATESTENABLE] ? 1 : 0);
if (context->rs[NINED3DRS_ALPHACOVERAGE] != alphacoverage_prev) if (context->rs[NINED3DRS_ALPHACOVERAGE] != alphacoverage_prev)
context->changed.group |= NINE_STATE_BLEND; context->changed.group |= NINE_STATE_BLEND;
} }