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i965/gen9: Set tiled resource mode for the miptree

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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Anuj Phogat 2015-04-14 22:06:47 -07:00
parent ef6b9985ea
commit 126078faca
2 changed files with 10 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_tex_layout.c
View file

@ -568,6 +568,8 @@ brw_miptree_layout(struct brw_context *brw,
{
bool gen6_hiz_or_stencil = false;
mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
const GLenum base_format = _mesa_get_format_base_format(mt->format);
gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);

8
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View file

@ -330,6 +330,13 @@ struct intel_miptree_aux_buffer
struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
};
/* Tile resource modes */
enum intel_miptree_tr_mode {
INTEL_MIPTREE_TRMODE_NONE,
INTEL_MIPTREE_TRMODE_YF,
INTEL_MIPTREE_TRMODE_YS
};
struct intel_mipmap_tree
{
/** Buffer object containing the pixel data. */
@ -338,6 +345,7 @@ struct intel_mipmap_tree
uint32_t pitch; /**< pitch in bytes. */
uint32_t tiling; /**< One of the I915_TILING_* flags */
enum intel_miptree_tr_mode tr_mode;
/* Effectively the key:
*/