diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index d3236c85e10..f72dda532f7 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -4124,11 +4124,10 @@ bool store_output_to_temps(isel_context *ctx, nir_intrinsic_instr *instr)
    unsigned component = nir_intrinsic_component(instr);
    unsigned idx = nir_intrinsic_base(instr) * 4u + component;
 
-   if (!nir_src_is_const(instr->src[1]))
+   if (!nir_src_is_const(instr->src[1]) || nir_src_as_uint(instr->src[1]))
       return false;
 
    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
-   idx += nir_src_as_uint(instr->src[1]) * 4u;
 
    if (instr->src[0].ssa->bit_size == 64)
       write_mask = widen_mask(write_mask, 2);
@@ -4510,13 +4509,12 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
 
-      if (!nir_src_is_const(instr->src[0]))
-         isel_err(instr->src[0].ssa->parent_instr, "Unimplemented non-const nir_intrinsic_load_input offset");
-      uint32_t offset = nir_src_as_uint(instr->src[0]);
+      if (!nir_src_is_const(instr->src[0]) || nir_src_as_uint(instr->src[0]))
+         isel_err(instr->src[0].ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
 
       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
 
-      unsigned location = nir_intrinsic_base(instr) - VERT_ATTRIB_GENERIC0 + offset;
+      unsigned location = nir_intrinsic_base(instr) - VERT_ATTRIB_GENERIC0;
       unsigned component = nir_intrinsic_component(instr);
       unsigned bitsize = instr->dest.ssa.bit_size;
       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];