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r600g: Set tiling information for BOs being shared.

Browse source 
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=48747
This commit is contained in:
Michel Dänzer 2012-05-16 17:45:17 +02:00 • committed by Michel Dänzer
parent 76d6a64de3
commit 11f056a3f0
3 changed files with 47 additions and 9 deletions
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12
src/gallium/drivers/r600/r600_texture.c
View file

@ -447,8 +447,20 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
struct radeon_surface *surface = &rtex->surface;
struct r600_screen *rscreen = (struct r600_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->bankw, surface->bankh,
surface->tile_split,
surface->stencil_tile_split,
surface->mtilea,
rtex->pitch_in_bytes[0]);
return rscreen->ws->buffer_get_handle(resource->buf,
rtex->pitch_in_bytes[0], whandle);
}

39
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
View file

@ -632,6 +632,20 @@ static unsigned eg_tile_split(unsigned tile_split)
return tile_split;
}
static unsigned eg_tile_split_rev(unsigned eg_tile_split)
{
switch (eg_tile_split) {
case 64: return 0;
case 128: return 1;
case 256: return 2;
case 512: return 3;
default:
case 1024: return 4;
case 2048: return 5;
case 4096: return 6;
}
}
static void radeon_bo_get_tiling(struct pb_buffer *_buf,
enum radeon_bo_layout *microtiled,
enum radeon_bo_layout *macrotiled,
@ -670,23 +684,19 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
}
static void radeon_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtiled,
enum radeon_bo_layout macrotiled,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
unsigned mtilea,
uint32_t pitch)
{
struct radeon_bo *bo = get_radeon_bo(_buf);
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct drm_radeon_gem_set_tiling args;
memset(&args, 0, sizeof(args));
/* Tiling determines how DRM treats the buffer data.
* We must flush CS when changing it if the buffer is referenced. */
if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
cs->flush_cs(cs->flush_data, 0);
}
while (p_atomic_read(&bo->num_active_ioctls)) {
sched_yield();
}
@ -699,6 +709,19 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
if (macrotiled == RADEON_LAYOUT_TILED)
args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
RADEON_TILING_EG_BANKW_SHIFT;
args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
RADEON_TILING_EG_BANKH_SHIFT;
args.tiling_flags |= (eg_tile_split_rev(tile_split) &
RADEON_TILING_EG_TILE_SPLIT_MASK) <<
RADEON_TILING_EG_TILE_SPLIT_SHIFT;
args.tiling_flags |= (stencil_tile_split &
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
args.handle = bo->handle;
args.pitch = pitch;

5
src/gallium/winsys/radeon/drm/radeon_winsys.h
View file

@ -219,9 +219,12 @@ struct radeon_winsys {
* \note microtile and macrotile are not bitmasks!
*/
void (*buffer_set_tiling)(struct pb_buffer *buf,
struct radeon_winsys_cs *cs,
enum radeon_bo_layout microtile,
enum radeon_bo_layout macrotile,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
unsigned mtilea,
unsigned stride);
/**