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nir,pan: Rework the pafrost tile load intrinsic
Instead of making it explicitly about outputs, this switchies it to being a NIR version of LD_TILE. It means we have to do a bit of work in NIR and add a builder helper but the end result is something much more versatile. Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39367>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
592963e941
commit
11b6cd2f2c
8 changed files with 91 additions and 62 deletions
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@ -1011,8 +1011,8 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
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case nir_intrinsic_bvh_stack_rtn_amd:
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case nir_intrinsic_cmat_load_shared_nv:
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case nir_intrinsic_cmat_mov_transpose_nv:
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case nir_intrinsic_load_converted_output_pan:
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case nir_intrinsic_load_readonly_output_pan:
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case nir_intrinsic_load_tile_pan:
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case nir_intrinsic_load_tile_res_pan:
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case nir_intrinsic_load_cumulative_coverage_pan:
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case nir_intrinsic_load_blend_input_pan:
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case nir_intrinsic_atest_pan:
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@ -1671,18 +1671,22 @@ intrinsic("load_frag_coord_zw_pan", [2], dest_comp=1, indices=[COMPONENT], flags
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# src[] = { sampler_index }
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load("sampler_lod_parameters", [1], flags=[CAN_ELIMINATE, CAN_REORDER])
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# Like load_output but using a specified render target and conversion descriptor
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# src[] = { target, sample, conversion }
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# target must be in the [0..7] range when io_semantics.location is FRAG_RESULT_DATA0
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# and is ignored otherwise
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load("converted_output_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE])
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# Maps to LD_TILE
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#
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# rt must be in the [0..7] range when and io_semantics.location is not
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# GL_FRAG_RESULT_DEPTH or GL_FRAG_RESULT_STENCIL
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#
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# src[] = { rt_sample_pixel, coverage_offset, conversion }
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load("tile_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS],
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flags=[CAN_ELIMINATE])
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# Like converted_output_pan but for case where the output is never written by the shader
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# This is used to relax waits on tile-buffer accesses and the target is read-only
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# src[] = { target, sample, conversion }
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# target must be in the [0..7] range when io_semantics.location is FRAG_RESULT_DATA0
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# and is ignored otherwise
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load("readonly_output_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE])
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# Like load_tile_pan except it relies on resource tracking through
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# resource_read/write_mask for dependencies instead of ensuring absolute
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# pixel ordering like load_tile_pan does.
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#
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# src[] = { rt_sample_pixel, coverage_offset, conversion }
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load("tile_res_pan", [1, 1, 1], indices=[ACCESS, DEST_TYPE, IO_SEMANTICS],
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flags=[CAN_ELIMINATE, CAN_REORDER])
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# Load converted memory given an address and a conversion descriptor
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# src[] = { address, conversion }
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@ -412,8 +412,8 @@ nir_lower_non_uniform_access_impl(nir_function_impl *impl,
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progress = true;
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break;
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case nir_intrinsic_load_readonly_output_pan:
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case nir_intrinsic_load_converted_output_pan:
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case nir_intrinsic_load_tile_pan:
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case nir_intrinsic_load_tile_res_pan:
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/* render target can be nonuniform, but not conversion descriptor */
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if ((options->types & nir_lower_non_uniform_image_access) &&
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lower_non_uniform_access_intrin(&state, intrin, 2, nir_lower_non_uniform_image_access))
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@ -1475,8 +1475,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state)
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_load_converted_output_pan:
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case nir_intrinsic_load_readonly_output_pan:
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case nir_intrinsic_load_tile_pan:
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case nir_intrinsic_load_tile_res_pan:
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case nir_intrinsic_load_per_primitive_output:
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_primitive_output:
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@ -1928,40 +1928,19 @@ bi_emit_ld_tile(bi_builder *b, nir_intrinsic_instr *instr)
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bi_index dest = bi_def_index(&instr->def);
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nir_alu_type T = nir_intrinsic_dest_type(instr);
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nir_io_semantics sem = nir_intrinsic_io_semantics(instr);
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bool is_zs = bi_is_zs(sem.location);
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enum bi_register_format regfmt = bi_reg_fmt_for_nir(T);
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unsigned size = instr->def.bit_size;
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unsigned nr = instr->num_components;
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unsigned target = 0, sample = 0;
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if (sem.location == FRAG_RESULT_DEPTH) {
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target = 255;
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} else if (sem.location == FRAG_RESULT_STENCIL) {
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target = 254;
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} else if (nir_src_is_const(instr->src[0])) {
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target = nir_src_as_uint(instr->src[0]);
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assert(target < 8);
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}
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bi_index pi = bi_src_index(&instr->src[0]);
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bi_index coverage = bi_src_index(&instr->src[1]);
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bi_index conversion = bi_src_index(&instr->src[2]);
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if (nir_src_is_const(instr->src[1]))
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sample = nir_src_as_uint(instr->src[1]);
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bi_instr *I = bi_ld_tile_to(b, dest, pi, coverage, conversion,
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regfmt, nr - 1);
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I->z_stencil = bi_is_zs(sem.location);
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bi_index pi = bi_pixel_indices(b, target, sample);
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if (!is_zs && !nir_src_is_const(instr->src[0]))
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pi = bi_lshift_or(b, 32, bi_src_index(&instr->src[0]), pi, bi_imm_u8(8));
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if (!nir_src_is_const(instr->src[1])) {
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pi = bi_mux_i32(b, bi_src_index(&instr->src[1]), pi,
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bi_imm_u32(0x1f), BI_MUX_BIT);
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}
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bi_instr *I = bi_ld_tile_to(b, dest, pi, bi_coverage(b),
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bi_src_index(&instr->src[2]), regfmt, nr - 1);
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if (is_zs)
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I->z_stencil = true;
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if (instr->intrinsic == nir_intrinsic_load_readonly_output_pan)
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if (instr->intrinsic == nir_intrinsic_load_tile_res_pan)
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I->wait_resource = true;
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bi_emit_cached_split(b, dest, size * nr);
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@ -2378,8 +2357,8 @@ bi_emit_intrinsic(bi_builder *b, nir_intrinsic_instr *instr)
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bi_emit_store_converted_mem(b, instr);
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break;
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case nir_intrinsic_load_converted_output_pan:
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case nir_intrinsic_load_readonly_output_pan:
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case nir_intrinsic_load_tile_pan:
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case nir_intrinsic_load_tile_res_pan:
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bi_emit_ld_tile(b, instr);
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break;
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@ -6184,9 +6163,11 @@ bi_lower_load_output(nir_builder *b, nir_intrinsic_instr *intr,
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nir_def *conversion = nir_load_rt_conversion_pan(
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b, .base = rt, .src_type = nir_intrinsic_dest_type(intr));
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nir_def *lowered = nir_load_converted_output_pan(
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b, intr->def.num_components, intr->def.bit_size, nir_imm_int(b, rt),
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nir_imm_int(b, 0), conversion, .dest_type = nir_intrinsic_dest_type(intr),
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nir_def *lowered = nir_load_tile_pan(
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b, intr->def.num_components, intr->def.bit_size,
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pan_nir_tile_location_sample(b, loc, nir_imm_int(b, 0)),
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pan_nir_tile_default_coverage(b),
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conversion, .dest_type = nir_intrinsic_dest_type(intr),
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.io_semantics = nir_intrinsic_io_semantics(intr));
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nir_def_rewrite_uses(&intr->def, lowered);
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@ -26,10 +26,44 @@
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#define __PAN_NIR_H__
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#include "nir.h"
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#include "nir_builder.h"
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#include "pan_compiler.h"
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struct util_format_description;
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static inline nir_def *
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pan_nir_tile_rt_sample(nir_builder *b, nir_def *rt, nir_def *sample)
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{
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/* y = 255 means "current pixel" */
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return nir_pack_32_4x8_split(b, nir_u2u8(b, sample),
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nir_u2u8(b, rt),
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nir_imm_intN_t(b, 0, 8),
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nir_imm_intN_t(b, 255, 8));
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}
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static inline nir_def *
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pan_nir_tile_location_sample(nir_builder *b, gl_frag_result location,
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nir_def *sample)
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{
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uint8_t rt;
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if (location == FRAG_RESULT_DEPTH) {
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rt = 255;
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} else if (location == FRAG_RESULT_STENCIL) {
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rt = 254;
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} else {
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assert(location >= FRAG_RESULT_DATA0);
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rt = location - FRAG_RESULT_DATA0;
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}
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return pan_nir_tile_rt_sample(b, nir_imm_int(b, rt), sample);
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}
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static inline nir_def *
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pan_nir_tile_default_coverage(nir_builder *b)
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{
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return nir_iand_imm(b, nir_load_cumulative_coverage_pan(b), 0x1f);
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}
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bool pan_nir_lower_store_component(nir_shader *shader);
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bool pan_nir_lower_vertex_id(nir_shader *shader);
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@ -812,10 +812,13 @@ lower_rt_intrin(nir_builder *b, nir_intrinsic_instr *intr, void *data)
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b->cursor = nir_after_instr(&intr->instr);
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nir_def *lowered = nir_load_converted_output_pan(
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nir_def *sample_id =
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nr_samples > 1 ? nir_load_sample_id(b) : nir_imm_int(b, 0);
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nir_def *lowered = nir_load_tile_pan(
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b, intr->def.num_components, intr->def.bit_size,
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nir_imm_int(b, rt),
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nr_samples > 1 ? nir_load_sample_id(b) : nir_imm_int(b, 0),
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pan_nir_tile_rt_sample(b, nir_imm_int(b, rt), sample_id),
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pan_nir_tile_default_coverage(b),
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nir_imm_int(b, blend_desc >> 32),
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.dest_type = dest_type,
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.io_semantics = io);
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@ -34,6 +34,7 @@
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#include "nir.h"
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#include "nir_builder.h"
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#include "pan_nir.h"
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struct panvk_lower_input_attachment_load_ctx {
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uint32_t ro_color_mask;
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@ -161,16 +162,20 @@ lower_input_attachment_load(nir_builder *b, nir_intrinsic_instr *intr,
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iosem.location = FRAG_RESULT_DATA0;
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nir_push_if(b, is_read_only);
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{
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load_ro_color = nir_load_readonly_output_pan(
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b, intr->def.num_components, intr->def.bit_size, target,
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intr->src[2].ssa, conversion, .dest_type = dest_type,
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load_ro_color = nir_load_tile_res_pan(
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b, intr->def.num_components, intr->def.bit_size,
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pan_nir_tile_rt_sample(b, target, intr->src[2].ssa),
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pan_nir_tile_default_coverage(b),
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conversion, .dest_type = dest_type,
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.access = nir_intrinsic_access(intr), .io_semantics = iosem);
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}
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nir_push_else(b, NULL);
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{
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load_rw_color = nir_load_converted_output_pan(
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b, intr->def.num_components, intr->def.bit_size, target,
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intr->src[2].ssa, conversion, .dest_type = dest_type,
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load_rw_color = nir_load_tile_pan(
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b, intr->def.num_components, intr->def.bit_size,
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pan_nir_tile_rt_sample(b, target, intr->src[2].ssa),
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pan_nir_tile_default_coverage(b),
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conversion, .dest_type = dest_type,
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.access = nir_intrinsic_access(intr), .io_semantics = iosem);
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}
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nir_pop_if(b, NULL);
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@ -201,9 +206,11 @@ lower_input_attachment_load(nir_builder *b, nir_intrinsic_instr *intr,
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iosem.location = dest_type == nir_type_float32 ? FRAG_RESULT_DEPTH
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: FRAG_RESULT_STENCIL;
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target = nir_imm_int(b, 0);
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load_zs = nir_load_converted_output_pan(
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b, intr->def.num_components, intr->def.bit_size, target,
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intr->src[2].ssa, conversion, .dest_type = dest_type,
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load_zs = nir_load_tile_pan(
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b, intr->def.num_components, intr->def.bit_size,
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pan_nir_tile_location_sample(b, iosem.location, intr->src[2].ssa),
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pan_nir_tile_default_coverage(b),
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conversion, .dest_type = dest_type,
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.access = nir_intrinsic_access(intr), .io_semantics = iosem);
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/* If we loaded the stencil value, the upper 24 bits might contain
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