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intel/eu: Set scope to TILE for TGM flushes

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Setting it to GPU can cause an L3$ flush in certain cases.  That's not
what we want as we really only care about coherency within the GPU.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12291>
This commit is contained in:
Jason Ekstrand 2021-08-09 17:23:52 -05:00 • committed by Marge Bot
parent 96403c1ec4
commit 11ac7d9e02
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_eu_emit.c
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@ -3251,7 +3251,7 @@ gfx12_set_memory_fence_message(struct brw_codegen *p,
enum lsc_flush_type flush_type = LSC_FLUSH_TYPE_NONE;
if (sfid == GFX12_SFID_TGM) {
scope = LSC_FENCE_GPU;
scope = LSC_FENCE_TILE;
flush_type = LSC_FLUSH_TYPE_EVICT;
}