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i965: SNB GT1 has only 32k urb and max 128 urb entries.

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Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
This commit is contained in:
Zou Nan hai 2011-03-03 10:30:06 +08:00
parent 2e756f3d6f
commit 118ecb1a22
2 changed files with 19 additions and 4 deletions
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19
src/mesa/drivers/dri/i965/gen6_urb.c
View file

@ -34,15 +34,26 @@
static void
prepare_urb( struct brw_context *brw )
{
brw->urb.nr_vs_entries = 256;
brw->urb.nr_gs_entries = 256;
int urb_size, max_urb_entry;
struct intel_context *intel = &brw->intel;
if (IS_GT1(intel->intelScreen->deviceID)) {
urb_size = 32 * 1024;
max_urb_entry = 128;
} else {
urb_size = 64 * 1024;
max_urb_entry = 256;
}
brw->urb.nr_vs_entries = max_urb_entry;
brw->urb.nr_gs_entries = max_urb_entry;
/* CACHE_NEW_VS_PROG */
brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
if (256 * brw->urb.vs_size > 64 * 1024)
if (2 * brw->urb.vs_size > urb_size)
brw->urb.nr_vs_entries = brw->urb.nr_gs_entries =
(64 * 1024 ) / brw->urb.vs_size;
(urb_size ) / (2 * brw->urb.vs_size);
}
static void

4
src/mesa/drivers/dri/intel/intel_chipset.h
View file

@ -133,6 +133,10 @@
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_S)
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
IS_GEN5(devid) || \