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radeon: Drop the unused first arg of OUT_BATCH_RELOC.

Browse source 
This was a trap when trying to figure out how to fit data bits into
the reloc.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Eric Anholt 2019-09-05 16:06:34 -07:00
parent 2a548cf92f
commit 1165e3f360
9 changed files with 24 additions and 24 deletions
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6
src/mesa/drivers/dri/r200/r200_blit.c
View file

@ -302,7 +302,7 @@ static void inline emit_tx_setup(struct r200_context *r200,
OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32);
OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
END_BATCH();
}
@ -367,9 +367,9 @@ static inline void emit_cb_setup(struct r200_context *r200,
OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}

2
src/mesa/drivers/dri/r200/r200_cmdbuf.c
View file

@ -232,7 +232,7 @@ void r200EmitVertexAOS( r200ContextPtr rmesa,
OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
}

2
src/mesa/drivers/dri/r200/r200_context.c
View file

@ -149,7 +149,7 @@ static void r200_emit_query_finish(radeonContextPtr radeon)
BEGIN_BATCH(4);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_BATCH_RELOC(query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_BATCH();
query->curr_offset += sizeof(uint32_t);
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);

12
src/mesa/drivers/dri/r200/r200_state_init.c
View file

@ -496,7 +496,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (drb) {
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
OUT_BATCH(zbpitch);
@ -511,10 +511,10 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (rrb) {
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
}
if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
@ -581,11 +581,11 @@ static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom)
if (dwords > atom->cmd_size) {
OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
if (t->mt && !t->image_override) {
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, t->tile_bits,
OUT_BATCH_RELOC(t->mt->bo, t->tile_bits,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else {
if (t->bo)
OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits,
OUT_BATCH_RELOC(t->bo, t->tile_bits,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
}
}
@ -610,7 +610,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
lvl = &t->mt->levels[0];
for (j = 1; j <= 5; j++) {
OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
OUT_BATCH_RELOC(t->mt->bo, lvl->faces[j].offset,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
}
}

6
src/mesa/drivers/dri/radeon/radeon_blit.c
View file

@ -153,7 +153,7 @@ static void inline emit_tx_setup(struct r100_context *r100,
OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1);
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
END_BATCH();
}
@ -215,9 +215,9 @@ static inline void emit_cb_setup(struct r100_context *r100,
OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}

2
src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
View file

@ -44,7 +44,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
/**
* Write a relocated dword to the command buffer.
*/
#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
#define OUT_BATCH_RELOC(bo, offset, rd, wd, flags) \
do { \
int __offset = (offset); \
if (0 && __offset) { \

2
src/mesa/drivers/dri/radeon/radeon_context.c
View file

@ -114,7 +114,7 @@ static void r100_emit_query_finish(radeonContextPtr radeon)
BEGIN_BATCH(4);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_BATCH_RELOC(query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_BATCH();
query->curr_offset += sizeof(uint32_t);
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);

2
src/mesa/drivers/dri/radeon/radeon_ioctl.c
View file

@ -290,7 +290,7 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa,
OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
#endif

14
src/mesa/drivers/dri/radeon/radeon_state_init.c
View file

@ -378,7 +378,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (drb) {
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
OUT_BATCH(zbpitch);
@ -392,10 +392,10 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (rrb) {
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_RELOC(rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
}
// if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
@ -447,7 +447,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
lvl = &t->mt->levels[0];
for (j = 0; j < 5; j++) {
OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
OUT_BATCH_RELOC(t->mt->bo, lvl->faces[j].offset,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
}
END_BATCH();
@ -485,16 +485,16 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
if (ctx->Texture.Unit[i]._Current &&
ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
lvl = &t->mt->levels[t->minLod];
OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
OUT_BATCH_RELOC(t->mt->bo, lvl->faces[5].offset,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else {
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo,
OUT_BATCH_RELOC(t->mt->bo,
get_base_teximage_offset(t) | t->tile_bits,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
}
} else {
if (t->bo)
OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits,
OUT_BATCH_RELOC(t->bo, t->tile_bits,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
}
}