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aco: preserve bitsets after a lane mask is written

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fossil-db (navi31):
Totals from 4840 (6.10% of 79395) affected shaders:
Instrs: 13733449 -> 13761177 (+0.20%); split: -0.00%, +0.21%
CodeSize: 71997868 -> 72102520 (+0.15%); split: -0.00%, +0.15%
Latency: 128385177 -> 128408780 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 21105847 -> 21109475 (+0.02%); split: -0.00%, +0.02%
VALU: 7741209 -> 7741210 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
This commit is contained in:
Rhys Perry 2024-08-22 20:22:00 +01:00 • committed by Marge Bot
parent 61e73c2323
commit 11262a01ce
2 changed files with 7 additions and 2 deletions
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5
src/amd/compiler/aco_insert_NOPs.cpp
View file

@ -1468,8 +1468,9 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr<Instruction>&
if (state.program->wave_size == 64 && instr->isSALU() &&
check_written_regs(instr, ctx.sgpr_read_by_valu_as_lanemask)) {
ctx.sgpr_read_by_valu_as_lanemask_then_wr_by_salu = ctx.sgpr_read_by_valu_as_lanemask;
ctx.sgpr_read_by_valu_as_lanemask.reset();
unsigned reg = instr->definitions[0].physReg().reg();
for (unsigned i = 0; i < instr->definitions[0].size(); i++)
ctx.sgpr_read_by_valu_as_lanemask_then_wr_by_salu[reg + i] = 1;
}
if (instr->isVALU()) {

4
src/amd/compiler/tests/test_insert_nops.cpp
View file

@ -1648,6 +1648,8 @@ BEGIN_TEST(insert_nops.setpc_gfx11)
//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:vcc
//! s1: %0:vcc_hi = s_mov_b32 0
//! s_waitcnt_depctr va_vdst(0) sa_sdst(0)
//! v1: %0:v[0] = v_xor3_b32 %0:v[0], %0:s[0], %0:s[0]
//! s_waitcnt_depctr va_vdst(0)
//! s_setpc_b64 0
bld.pseudo(aco_opcode::p_unit_test, Operand::c32(4));
bld.vop2(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
@ -1670,6 +1672,8 @@ BEGIN_TEST(insert_nops.setpc_gfx11)
//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:vcc
//! s2: %0:vcc = s_mov_b64 0
//! s_waitcnt_depctr va_vdst(0) sa_sdst(0)
//! v1: %0:v[0] = v_xor3_b32 %0:v[0], %0:s[0], %0:s[0]
//! s_waitcnt_depctr va_vdst(0)
//! s_setpc_b64 0
bld.pseudo(aco_opcode::p_unit_test, Operand::c32(5));
bld.vop2(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),