From 10ef9c6a80f58c9e20099dcc5f64c6d953174e9f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 19 Jun 2025 11:38:44 +0200 Subject: [PATCH] radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5 This looks like a hw bug on GFX10.3-GFX11.5 because RB+ seems to only work as expected when all channels (RGBA) are written. With that format, RGB channels must be all set or unset but setting the A channel is legal so far. This will reduce rendering performance with that format but it's the less intrusive solution for now. This might be revisited in the near future, also with more VKCTS coverage. This has been tested and verified on GFX10.3 (NAVI21) and GFX11 (NAVI31) and GFX12 (NAVI48), unfortunately I don't have GFX11.5 but let's assume it's broken there too. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13371 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6e801aaeeb4..a9569549842 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1944,8 +1944,20 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) } break; case V_028C70_COLOR_5_9_9_9: - if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) - sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4); + if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { + if (pdev->info.gfx_level >= GFX12) { + sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4); + } else if (pdev->info.gfx_level >= GFX10_3) { + if (colormask == 0xf) { + sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4); + } else { + /* On GFX10_3+, RB+ with E5B9G9R9 seems broken in the hardware when not all + * channels are written. Disable RB+ to workaround it. + */ + sx_ps_downconvert |= V_028754_SX_RT_EXPORT_NO_CONVERSION << (i * 4); + } + } + } break; } }