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radeon/r200/r300: another big merge upheavel.

Browse source 
This merges lots of the hw state atom emission and firevertices code.

it also removes a lot of the extra radeon crap from r300

and merge scissor
This commit is contained in:
Dave Airlie 2009-02-12 21:16:39 +10:00
parent f3f1f7dc20
commit 1090d206de
44 changed files with 356 additions and 1269 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

193
src/mesa/drivers/dri/r200/r200_cmdbuf.c
View file

@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_sanity.h"
#include "radeon_reg.h"
#define DEBUG_CMDBUF 0
/* The state atoms will be emitted in the order they appear in the atom list,
* so this step is important.
*/
@ -58,161 +56,54 @@ void r200SetUpAtomList( r200ContextPtr rmesa )
mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
make_empty_list(&rmesa->hw.atomlist);
rmesa->hw.atomlist.name = "atom-list";
make_empty_list(&rmesa->radeon.hw.atomlist);
rmesa->radeon.hw.atomlist.name = "atom-list";
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ctx );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.set );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lin );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msk );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpt );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vtx );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vap );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vte );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msc );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cst );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.zbs );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcl );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msl );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcg );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.grd );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.fog );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tam );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tf );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.atf );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf );
for (i = 0; i < mtu; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tex[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] );
for (i = 0; i < mtu; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cube[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] );
for (i = 0; i < 6; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pix[i] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[0] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[1] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
for (i = 0; i < 8; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lit[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
for (i = 0; i < 3 + mtu; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mat[i] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.eye );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.glt );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt );
for (i = 0; i < 2; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] );
for (i = 0; i < 6; ++i)
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.spr );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ptp );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.prf );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pvs );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[0] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[1] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[0] );
insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[1] );
}
static void r200SaveHwState( r200ContextPtr rmesa )
{
struct radeon_state_atom *atom;
char * dest = rmesa->backup_store.cmd_buf;
uint32_t dwords;
if (R200_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s\n", __FUNCTION__);
rmesa->backup_store.cmd_used = 0;
foreach( atom, &rmesa->hw.atomlist ) {
dwords = atom->check( rmesa->radeon.glCtx, atom );
if ( dwords ) {
int size = atom->cmd_size * 4;
if (atom->emit) {
(*atom->emit)(rmesa->radeon.glCtx, atom);
} else {
memcpy( dest, atom->cmd, size);
dest += size;
rmesa->backup_store.cmd_used += size;
}
if (R200_DEBUG & DEBUG_STATE)
radeon_print_state_atom( atom );
}
}
assert( rmesa->backup_store.cmd_used <= R200_CMD_BUF_SZ );
if (R200_DEBUG & DEBUG_STATE)
fprintf(stderr, "Returning to r200EmitState\n");
}
static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty)
{
BATCH_LOCALS(&r200->radeon);
struct radeon_state_atom *atom;
int dwords;
/* Emit actual atoms */
foreach(atom, &r200->hw.atomlist) {
if ((atom->dirty || r200->hw.all_dirty) == dirty) {
dwords = (*atom->check) (r200->radeon.glCtx, atom);
if (dwords) {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
radeon_print_state_atom(atom);
}
if (atom->emit) {
(*atom->emit)(r200->radeon.glCtx, atom);
} else {
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
}
atom->dirty = GL_FALSE;
} else {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
fprintf(stderr, " skip state %s\n",
atom->name);
}
}
}
}
COMMIT_BATCH();
}
void r200EmitState( r200ContextPtr rmesa )
{
char *dest;
int mtu;
struct radeon_state_atom *atom;
uint32_t dwords;
if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
fprintf(stderr, "%s\n", __FUNCTION__);
if (rmesa->save_on_next_emit) {
r200SaveHwState(rmesa);
rmesa->save_on_next_emit = GL_FALSE;
}
if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
return;
mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
/* To avoid going across the entire set of states multiple times, just check
* for enough space for the case of emitting all state, and inline the
* r200AllocCmdBuf code here without all the checks.
*/
rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__);
if (!rmesa->radeon.cmdbuf.cs->cdw) {
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin reemit state\n");
r200EmitAtoms(rmesa, GL_FALSE);
}
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin dirty state\n");
r200EmitAtoms(rmesa, GL_TRUE);
rmesa->hw.is_dirty = GL_FALSE;
rmesa->hw.all_dirty = GL_FALSE;
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] );
insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] );
}
/* Fire a section of the retained (indexed_verts) buffer as a regular
@ -227,7 +118,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
assert(!(primitive & R200_VF_PRIM_WALK_IND));
r200EmitState( rmesa );
radeonEmitState(&rmesa->radeon);
if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
@ -313,7 +204,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
assert((primitive & R200_VF_PRIM_WALK_IND));
r200EmitState( rmesa );
radeonEmitState(&rmesa->radeon);
rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
0, R200_ELT_BUF_SZ, 4,

32
src/mesa/drivers/dri/r200/r200_context.c
View file

@ -61,6 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_maos.h"
#include "r200_vertprog.h"
#include "radeon_span.h"
#define need_GL_ARB_multisample
#define need_GL_ARB_texture_compression
#define need_GL_ARB_vertex_buffer_object
@ -259,43 +261,17 @@ static void r200_get_lock(radeonContextPtr radeon)
}
}
static void r200_vtbl_flush(GLcontext *ctx)
{
R200_FIREVERTICES(R200_CONTEXT(ctx));
}
static void r200_vtbl_flush_vertices(radeonContextPtr rmesa)
{
R200_FIREVERTICES(((r200ContextPtr)rmesa));
}
static void r200_vtbl_set_all_dirty(GLcontext *ctx)
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
rmesa->hw.all_dirty = GL_TRUE;
}
static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
}
static void r200_vtbl_emit_state(radeonContextPtr rmesa)
{
r200EmitState((r200ContextPtr)rmesa);
}
static void r200_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r200_get_lock;
radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
radeon->vtbl.flush = r200_vtbl_flush;
radeon->vtbl.flush_vertices = r200_vtbl_flush_vertices;
radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty;
radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer;
radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
radeon->vtbl.emit_state = r200_vtbl_emit_state;
radeon->vtbl.swtcl_flush = r200_swtcl_flush;
}
@ -390,7 +366,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->hw.all_dirty = 1;
rmesa->radeon.hw.all_dirty = 1;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
@ -565,7 +541,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
/* check if we're deleting the currently bound context */
if (rmesa == current) {
R200_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
_mesa_make_current(NULL, NULL, NULL);
}

14
src/mesa/drivers/dri/r200/r200_context.h
View file

@ -469,9 +469,6 @@ struct r200_texture_state {
struct r200_hw_state {
/* Head of the linked list of state atoms. */
struct radeon_state_atom atomlist;
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
* - reviving state after loss of context
@ -512,9 +509,6 @@ struct r200_hw_state {
struct radeon_state_atom atf;
struct radeon_state_atom spr;
struct radeon_state_atom ptp;
int max_state_size; /* Number of bytes necessary for a full state emit. */
GLboolean is_dirty, all_dirty;
};
struct r200_state {
@ -600,16 +594,10 @@ struct r200_context {
*/
struct radeon_ioctl ioctl;
struct radeon_store store;
/* A full state emit as of the first state emit in the main store, in case
* the context is lost.
*/
struct radeon_store backup_store;
/* Clientdata textures;
*/
GLuint prefer_gart_client_texturing;
GLboolean save_on_next_emit;
GLuint prefer_gart_client_texturing;
/* TCL stuff
*/

61
src/mesa/drivers/dri/r200/r200_ioctl.c
View file

@ -57,34 +57,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R200_TIMEOUT 512
#define R200_IDLE_RETRY 16
/* At this point we were in FlushCmdBufLocked but we had lost our context, so
* we need to unwire our current cmdbuf, hook the one with the saved state in
* it, flush it, and then put the current one back. This is so commands at the
* start of a cmdbuf can rely on the state being kept from the previous one.
*/
static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa )
{
GLuint nr_released_bufs;
struct radeon_store saved_store;
if (rmesa->backup_store.cmd_used == 0)
return;
if (R200_DEBUG & DEBUG_STATE)
fprintf(stderr, "Emitting backup state on lost context\n");
rmesa->radeon.lost_context = GL_FALSE;
nr_released_bufs = rmesa->radeon.dma.nr_released_bufs;
saved_store = rmesa->store;
rmesa->radeon.dma.nr_released_bufs = 0;
rmesa->store = rmesa->backup_store;
rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
rmesa->radeon.dma.nr_released_bufs = nr_released_bufs;
rmesa->store = saved_store;
}
static void r200UserClear(GLcontext *ctx, GLuint flags)
{
if (flags & (RADEON_FRONT | RADEON_BACK)) {
@ -291,36 +263,9 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
else
r200KernelClear(ctx, flags);
rmesa->hw.all_dirty = GL_TRUE;
rmesa->radeon.hw.all_dirty = GL_TRUE;
}
void r200Flush( GLcontext *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
if (R200_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
if (rmesa->radeon.dma.flush)
rmesa->radeon.dma.flush( ctx );
r200EmitState( rmesa );
if (rmesa->radeon.cmdbuf.cs->cdw)
rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
/* Make sure all commands have been sent to the hardware and have
* completed processing.
*/
void r200Finish( GLcontext *ctx )
{
r200Flush( ctx );
radeon_common_finish(ctx);
}
/* This version of AllocateMemoryMESA allocates only GART memory, and
* only does so after the point at which the driver has been
* initialized.
@ -458,7 +403,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
void r200InitIoctlFuncs( struct dd_function_table *functions )
{
functions->Clear = r200Clear;
functions->Finish = r200Finish;
functions->Flush = r200Flush;
functions->Finish = radeonFinish;
functions->Flush = radeonFlush;
}

14
src/mesa/drivers/dri/r200/r200_ioctl.h
View file

@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "common_cmdbuf.h"
extern void r200EmitState( r200ContextPtr rmesa );
extern void r200EmitVertexAOS( r200ContextPtr rmesa,
GLuint vertex_size,
struct radeon_bo *bo,
@ -101,7 +100,7 @@ do { \
do { \
R200_NEWPRIM( rmesa ); \
rmesa->hw.ATOM.dirty = GL_TRUE; \
rmesa->hw.is_dirty = GL_TRUE; \
rmesa->radeon.hw.is_dirty = GL_TRUE; \
} while (0)
#define R200_DB_STATE( ATOM ) \
@ -116,7 +115,7 @@ static INLINE int R200_DB_STATECHANGE(
GLuint *tmp;
R200_NEWPRIM( rmesa );
atom->dirty = GL_TRUE;
rmesa->hw.is_dirty = GL_TRUE;
rmesa->radeon.hw.is_dirty = GL_TRUE;
tmp = atom->cmd;
atom->cmd = atom->lastcmd;
atom->lastcmd = tmp;
@ -127,15 +126,6 @@ static INLINE int R200_DB_STATECHANGE(
}
/* Fire the buffered vertices no matter what.
*/
#define R200_FIREVERTICES( rmesa ) \
do { \
if ( rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \
r200Flush( rmesa->radeon.glCtx ); \
} \
} while (0)
/* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
* are available, you will also be adding an rmesa->state.max_state_size because
* r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.

29
src/mesa/drivers/dri/r200/r200_state.c
View file

@ -524,25 +524,6 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
}
}
/* =============================================================
* Scissoring
*/
static void r200Scissor( GLcontext *ctx,
GLint x, GLint y, GLsizei w, GLsizei h )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
if ( ctx->Scissor.Enabled ) {
R200_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */
radeonUpdateScissor( ctx );
}
}
/* =============================================================
* Culling
*/
@ -787,7 +768,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask )
/* TODO: push this into cmd mechanism
*/
R200_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
LOCK_HARDWARE( &rmesa->radeon );
/* FIXME: Use window x,y offsets into stipple RAM.
@ -1638,7 +1619,7 @@ void r200UpdateWindow( GLcontext *ctx )
float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
R200_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
R200_STATECHANGE( rmesa, vpt );
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
@ -1783,7 +1764,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode )
fprintf(stderr, "%s %s\n", __FUNCTION__,
_mesa_lookup_enum_by_nr( mode ));
R200_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */
if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
/* 0 (GL_NONE) buffers or multiple color drawing buffers */
@ -2057,7 +2038,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
}
case GL_SCISSOR_TEST:
R200_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
rmesa->radeon.state.scissor.enabled = state;
radeonUpdateScissor( ctx );
break;
@ -2575,7 +2556,7 @@ void r200InitStateFuncs( struct dd_function_table *functions )
functions->PointParameterfv = r200PointParameter;
functions->PointSize = r200PointSize;
functions->RenderMode = r200RenderMode;
functions->Scissor = r200Scissor;
functions->Scissor = radeonScissor;
functions->ShadeModel = r200ShadeModel;
functions->StencilFuncSeparate = r200StencilFuncSeparate;
functions->StencilMaskSeparate = r200StencilMaskSeparate;

15
src/mesa/drivers/dri/r200/r200_state_init.c
View file

@ -46,8 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_buffer.h"
#include "radeon_mipmap_tree.h"
#include "radeon_cs.h"
#include "common_context.h"
#include "common_cmdbuf.h"
#include "common_misc.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
@ -177,8 +176,8 @@ void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
fprintf(stderr, msg);
fprintf(stderr, ": ");
foreach(l, &rmesa->hw.atomlist) {
if (l->dirty || rmesa->hw.all_dirty)
foreach(l, &rmesa->radeon.hw.atomlist) {
if (l->dirty || rmesa->radeon.hw.all_dirty)
fprintf(stderr, "%s, ", l->name);
}
@ -649,7 +648,7 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch;
#endif
rmesa->hw.max_state_size = 0;
rmesa->radeon.hw.max_state_size = 0;
#define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
do { \
@ -660,7 +659,7 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.ATOM.idx = IDX; \
rmesa->hw.ATOM.check = check_##CHK; \
rmesa->hw.ATOM.dirty = GL_FALSE; \
rmesa->hw.max_state_size += SZ * sizeof(int); \
rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
} while (0)
@ -1405,7 +1404,7 @@ void r200InitState( r200ContextPtr rmesa )
r200LightingSpaceChange( ctx );
rmesa->hw.all_dirty = GL_TRUE;
rmesa->radeon.hw.all_dirty = GL_TRUE;
rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
rcommonInitCmdBuf(&rmesa->radeon);
}

10
src/mesa/drivers/dri/r200/r200_swtcl.c
View file

@ -204,8 +204,6 @@ static void r200SetVertexFormat( GLcontext *ctx )
static void r200RenderStart( GLcontext *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
r200SetVertexFormat( ctx );
}
@ -271,11 +269,11 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
rcommonEnsureCmdBufSpace(&rmesa->radeon,
rmesa->hw.max_state_size + (12*sizeof(int)),
rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
__FUNCTION__);
r200EmitState(rmesa);
radeonEmitState(&rmesa->radeon);
r200EmitVertexAOS( rmesa,
rmesa->radeon.swtcl.vertex_size,
rmesa->radeon.dma.current,
@ -649,7 +647,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode )
if (mode) {
rmesa->radeon.Fallback |= bit;
if (oldfallback == 0) {
R200_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE );
_swsetup_Wakeup( ctx );
rmesa->radeon.swtcl.RenderIndex = ~0;
@ -914,6 +912,4 @@ void r200InitSwtcl( GLcontext *ctx )
void r200DestroySwtcl( GLcontext *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
}

6
src/mesa/drivers/dri/r200/r200_tcl.c
View file

@ -123,7 +123,7 @@ static GLboolean discrete_prim[0x10] = {
#define RESET_STIPPLE() do { \
R200_STATECHANGE( rmesa, lin ); \
r200EmitState( rmesa ); \
radeonEmitState(&rmesa->radeon); \
} while (0)
#define AUTO_STIPPLE( mode ) do { \
@ -134,7 +134,7 @@ static GLboolean discrete_prim[0x10] = {
else \
rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
~R200_LINE_PATTERN_AUTO_RESET; \
r200EmitState( rmesa ); \
radeonEmitState(&rmesa->radeon); \
} while (0)
@ -189,7 +189,7 @@ static void r200EmitPrim( GLcontext *ctx,
// fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components);
rcommonEnsureCmdBufSpace( &rmesa->radeon,
AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
r200EmitAOS( rmesa,
rmesa->tcl.nr_aos_components,

2
src/mesa/drivers/dri/r200/r200_tex.c
View file

@ -420,7 +420,7 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
if (rmesa) {
int i;
R200_FIREVERTICES(rmesa);
radeon_firevertices(&rmesa->radeon);
for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
if ( t == rmesa->state.texture.unit[i].texobj ) {
rmesa->state.texture.unit[i].texobj = NULL;

4
src/mesa/drivers/dri/r300/Makefile
View file

@ -26,11 +26,7 @@ DRIVER_SOURCES = \
radeon_screen.c \
common_lock.c \
common_misc.c \
radeon_context.c \
radeon_ioctl.c \
radeon_span.c \
radeon_state.c \
r300_context.c \
r300_ioctl.c \
r300_cmdbuf.c \
r300_state.c \

119
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View file

@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_drm.h"
#include "radeon_buffer.h"
#include "radeon_ioctl.h"
#include "r300_context.h"
#include "r300_ioctl.h"
#include "radeon_reg.h"
@ -61,111 +60,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
# define RADEON_ONE_REG_WR (1 << 15)
// Set this to 1 for extremely verbose debugging of command buffers
#define DEBUG_CMDBUF 0
/** # of dwords reserved for additional instructions that may need to be written
* during flushing.
*/
#define SPACE_FOR_FLUSHING 4
static void r300PrintStateAtom(r300ContextPtr r300,
struct radeon_state_atom *state)
{
int i;
int dwords = (*state->check) (r300->radeon.glCtx, state);
fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
if (RADEON_DEBUG & DEBUG_VERBOSE) {
for (i = 0; i < dwords; i++) {
fprintf(stderr, " %s[%d]: %08x\n",
state->name, i, state->cmd[i]);
}
}
}
/**
* Emit all atoms with a dirty field equal to dirty.
*
* The caller must have ensured that there is enough space in the command
* buffer.
*/
static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
{
BATCH_LOCALS(&r300->radeon);
struct radeon_state_atom *atom;
int dwords;
cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1));
OUT_BATCH(R300_TX_FLUSH);
END_BATCH();
end_3d(r300);
/* Emit actual atoms */
foreach(atom, &r300->hw.atomlist) {
if ((atom->dirty || r300->hw.all_dirty) == dirty) {
dwords = (*atom->check) (r300->radeon.glCtx, atom);
if (dwords) {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
r300PrintStateAtom(r300, atom);
}
if (atom->emit) {
(*atom->emit)(r300->radeon.glCtx, atom);
} else {
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
}
atom->dirty = GL_FALSE;
} else {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
fprintf(stderr, " skip state %s\n",
atom->name);
}
}
}
}
COMMIT_BATCH();
}
/**
* Copy dirty hardware state atoms into the command buffer.
*
* We also copy out clean state if we're at the start of a buffer. That makes
* it easy to recover from lost contexts.
*/
void r300EmitState(r300ContextPtr r300)
{
if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
fprintf(stderr, "%s\n", __FUNCTION__);
if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty)
return;
/* To avoid going across the entire set of states multiple times, just check
* for enough space for the case of emitting all state.
*/
rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__);
if (!r300->radeon.cmdbuf.cs->cdw) {
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin reemit state\n");
r300EmitAtoms(r300, GL_FALSE);
}
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin dirty state\n");
r300EmitAtoms(r300, GL_TRUE);
r300->hw.is_dirty = GL_FALSE;
r300->hw.all_dirty = GL_FALSE;
}
static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
{
if (r300->radeon.radeonScreen->kernel_mm) {
@ -405,8 +304,8 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
r300->hw.ATOM.idx = (IDX); \
r300->hw.ATOM.check = check_##CHK; \
r300->hw.ATOM.dirty = GL_FALSE; \
r300->hw.max_state_size += (SZ); \
insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM); \
r300->radeon.hw.max_state_size += (SZ); \
insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
} while (0)
/**
* Allocate memory for the command buffer and initialize the state atom
@ -425,7 +324,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
r300->hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
if (RADEON_DEBUG & DEBUG_TEXTURE) {
@ -433,8 +332,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
}
/* Setup the atom linked list */
make_empty_list(&r300->hw.atomlist);
r300->hw.atomlist.name = "atom-list";
make_empty_list(&r300->radeon.hw.atomlist);
r300->radeon.hw.atomlist.name = "atom-list";
/* Initialize state atoms */
ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
@ -708,10 +607,10 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
r300->hw.is_dirty = GL_TRUE;
r300->hw.all_dirty = GL_TRUE;
r300->radeon.hw.is_dirty = GL_TRUE;
r300->radeon.hw.all_dirty = GL_TRUE;
rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size);
rcommonInitCmdBuf(&r300->radeon);
}
/**
@ -721,7 +620,7 @@ void r300DestroyCmdBuf(r300ContextPtr r300)
{
struct radeon_state_atom *atom;
foreach(atom, &r300->hw.atomlist) {
foreach(atom, &r300->radeon.hw.atomlist) {
FREE(atom->cmd);
}

32
src/mesa/drivers/dri/r300/r300_context.c
View file

@ -55,7 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "drivers/common/driverfuncs.h"
#include "radeon_ioctl.h"
#include "radeon_span.h"
#include "r300_context.h"
#include "r300_cmdbuf.h"
@ -198,22 +197,6 @@ static void r300_get_lock(radeonContextPtr rmesa)
}
}
static void r300_vtbl_flush(GLcontext *ctx)
{
r300Flush(ctx);
}
static void r300_vtbl_set_all_dirty(GLcontext *ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
rmesa->hw.all_dirty = GL_TRUE;
}
static void r300_vtbl_emit_state(radeonContextPtr rmesa)
{
r300EmitState((r300ContextPtr)rmesa);
}
static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
/* please flush pipe do all pending work */
@ -243,22 +226,25 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
R300_WAIT_3D | R300_WAIT_3D_CLEAN));
}
static void r300_vtbl_flush_vertices(radeonContextPtr rmesa)
static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
R300_FIREVERTICES(((r300ContextPtr)rmesa));
BATCH_LOCALS(radeon);
cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH(cmdpacket0(radeon->radeonScreen, R300_TX_INVALTAGS, 1));
OUT_BATCH(R300_TX_FLUSH);
END_BATCH();
end_3d(radeon);
}
static void r300_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r300_get_lock;
radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
radeon->vtbl.flush = r300_vtbl_flush;
radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty;
radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer;
radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
radeon->vtbl.emit_state = r300_vtbl_emit_state;
radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices;
radeon->vtbl.swtcl_flush = r300_swtcl_flush;
radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
}

9
src/mesa/drivers/dri/r300/r300_context.h
View file

@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_drm.h"
#include "dri_util.h"
#include "texmem.h"
#include "common_context.h"
#include "radeon_context.h"
#include "radeon_bo.h"
@ -53,7 +54,7 @@ struct r300_context;
typedef struct r300_context r300ContextRec;
typedef struct r300_context *r300ContextPtr;
#include "radeon_lock.h"
#include "main/mm.h"
/* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
@ -304,12 +305,6 @@ struct r300_texture_state {
* Cache for hardware register state.
*/
struct r300_hw_state {
struct radeon_state_atom atomlist;
GLboolean is_dirty;
GLboolean all_dirty;
int max_state_size; /* in dwords */
struct radeon_state_atom vpt; /* viewport (1D98) */
struct radeon_state_atom vap_cntl;
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */

1
src/mesa/drivers/dri/r300/r300_emit.c
View file

@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "tnl/t_context.h"
#include "r300_context.h"
#include "radeon_ioctl.h"
#include "r300_state.h"
#include "r300_emit.h"
#include "r300_ioctl.h"

40
src/mesa/drivers/dri/r300/r300_emit.h
View file

@ -146,36 +146,36 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
/**
* Must be sent to switch to 2d commands
*/
void static INLINE end_3d(r300ContextPtr rmesa)
void static INLINE end_3d(radeonContextPtr radeon)
{
BATCH_LOCALS(&rmesa->radeon);
BATCH_LOCALS(radeon);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen));
END_BATCH();
}
if (!radeon->radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdpacify(radeon->radeonScreen));
END_BATCH();
}
}
void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
{
BATCH_LOCALS(&rmesa->radeon);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
END_BATCH();
}
}
void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags)
{
BATCH_LOCALS(&rmesa->radeon);
uint32_t wait_until;
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags));
OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
END_BATCH();
}
}
void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
{
BATCH_LOCALS(radeon);
uint32_t wait_until;
if (!radeon->radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdwait(radeon->radeonScreen, flags));
END_BATCH();
} else {
switch(flags) {

7
src/mesa/drivers/dri/r300/r300_ioctl.c
View file

@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_buffer.h"
#include "r300_context.h"
#include "radeon_ioctl.h"
#include "r300_ioctl.h"
#include "r300_cmdbuf.h"
#include "r300_state.h"
@ -94,8 +93,8 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
}
/* TODO in bufmgr */
cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
end_3d(rmesa);
cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
end_3d(&rmesa->radeon);
if (flags & CLEARBUFFER_COLOR) {
assert(rrb != 0);
@ -195,7 +194,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
}
r300EmitCacheFlush(rmesa);
cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
R300_STATECHANGE(r300, cb);
R300_STATECHANGE(r300, cmk);

2
src/mesa/drivers/dri/r300/r300_render.c
View file

@ -66,8 +66,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "tnl/t_vp_build.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
#include "r300_context.h"
#include "r300_ioctl.h"
#include "r300_state.h"

16
src/mesa/drivers/dri/r300/r300_state.c
View file

@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "vbo/vbo.h"
#include "tnl/tnl.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
#include "radeon_buffer.h"
#include "r300_context.h"
#include "r300_ioctl.h"
@ -1087,7 +1085,7 @@ static void r300UpdateWindow(GLcontext * ctx)
GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale;
GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale;
R300_FIREVERTICES(rmesa);
radeon_firevertices(&rmesa->radeon);
R300_STATECHANGE(rmesa, vpt);
rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
@ -2112,6 +2110,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa)
*/
static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(cap),
@ -2157,8 +2156,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
case GL_POLYGON_OFFSET_FILL:
r300SetPolygonOffsetState(ctx, state);
break;
case GL_SCISSOR_TEST:
radeon_firevertices(&rmesa->radeon);
rmesa->radeon.state.scissor.enabled = state;
radeonUpdateScissor( ctx );
break;
default:
radeonEnable(ctx, cap, state);
break;
}
}
@ -2405,7 +2408,7 @@ static void r300ResetHwState(r300ContextPtr r300)
r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
}
r300->hw.all_dirty = GL_TRUE;
r300->radeon.hw.all_dirty = GL_TRUE;
}
void r300UpdateShaders(r300ContextPtr rmesa)
@ -2747,7 +2750,7 @@ static void r300DrawBuffer( GLcontext *ctx, GLenum mode )
fprintf(stderr, "%s %s\n", __FUNCTION__,
_mesa_lookup_enum_by_nr( mode ));
R300_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */
radeonSetCliprects( &rmesa->radeon );
radeonUpdatePageFlipping(&rmesa->radeon);
@ -2803,6 +2806,7 @@ void r300InitStateFuncs(struct dd_function_table *functions)
functions->RenderMode = r300RenderMode;
functions->ClipPlane = r300ClipPlane;
functions->Scissor = radeonScissor;
functions->DrawBuffer = r300DrawBuffer;
functions->ReadBuffer = r300ReadBuffer;

15
src/mesa/drivers/dri/r300/r300_state.h
View file

@ -39,26 +39,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R300_NEWPRIM( rmesa ) \
do { \
if ( rmesa->radeon.dma.flush ) \
rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
} while (0)
#define R300_STATECHANGE(r300, atom) \
do { \
R300_NEWPRIM(r300); \
r300->hw.atom.dirty = GL_TRUE; \
r300->hw.is_dirty = GL_TRUE; \
r300->radeon.hw.is_dirty = GL_TRUE; \
} while(0)
#define R300_PRINT_STATE(r300, atom) \
r300PrintStateAtom(r300, &r300->hw.atom)
/* Fire the buffered vertices no matter what.
TODO: This has not been implemented yet
*/
#define R300_FIREVERTICES( r300 ) \
do { \
r300Flush( (r300)->radeon.glCtx ); \
} while (0)
// r300_state.c
extern int future_hw_tcl_on;
void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx);

2
src/mesa/drivers/dri/r300/r300_swtcl.c
View file

@ -626,7 +626,7 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
r300ContextPtr rmesa = R300_CONTEXT(ctx);
rcommonEnsureCmdBufSpace(&rmesa->radeon,
rmesa->hw.max_state_size + (12*sizeof(int)),
rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
__FUNCTION__);
r300EmitState(rmesa);
r300EmitVertexAOS(rmesa,

2
src/mesa/drivers/dri/r300/r300_tex.c
View file

@ -263,7 +263,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
if (rmesa) {
int i;
R300_FIREVERTICES(rmesa);
radeon_firevertices(&rmesa->radeon);
for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i)
if (rmesa->hw.textures[i] == t)

58
src/mesa/drivers/dri/r300/r300_texmem.c
View file

@ -1,58 +0,0 @@
/**************************************************************************
Copyright (C) Tungsten Graphics 2002. All Rights Reserved.
The Weather Channel, Inc. funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86
license. This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation on the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Gareth Hughes <gareth@valinux.com>
*
* \author Kevin E. Martin <martin@valinux.com>
*/
#include <errno.h>
#include "main/glheader.h"
#include "main/imports.h"
#include "main/context.h"
#include "main/colormac.h"
#include "main/macros.h"
#include "main/simple_list.h"
#include "radeon_reg.h" /* gets definition for usleep */
#include "r300_context.h"
#include "r300_state.h"
#include "r300_cmdbuf.h"
#include "r300_emit.h"
#include "r300_mipmap_tree.h"
#include "radeon_ioctl.h"
#include "r300_tex.h"
#include "r300_ioctl.h"
#include <unistd.h> /* for usleep() */

1
src/mesa/drivers/dri/r300/r300_texstate.c
View file

@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r300_context.h"
#include "r300_state.h"
#include "r300_ioctl.h"
#include "radeon_ioctl.h"
#include "radeon_mipmap_tree.h"
#include "radeon_cs.h"
#include "r300_tex.h"

75
src/mesa/drivers/dri/r300/radeon_context.c
View file

@ -1,75 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file radeon_context.c
* Common context initialization.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include <dlfcn.h>
#include "main/glheader.h"
#include "main/imports.h"
#include "main/context.h"
#include "main/state.h"
#include "main/matrix.h"
#include "main/framebuffer.h"
#include "drivers/common/driverfuncs.h"
#include "swrast/swrast.h"
#include "radeon_buffer.h"
#include "radeon_screen.h"
#include "radeon_ioctl.h"
#include "radeon_macros.h"
#include "radeon_reg.h"
#include "radeon_state.h"
#include "r300_state.h"
#include "utils.h"
#include "vblank.h"
#include "xmlpool.h" /* for symbolic values of enum-type options */
#include "drirenderbuffer.h"
/* Force the context `c' to be unbound from its buffer.
*/
GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
{
radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
radeon->glCtx);
return GL_TRUE;
}

43
src/mesa/drivers/dri/r300/radeon_context.h
View file

@ -67,20 +67,6 @@ extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
/* TCL fallbacks */
extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
#define RADEON_TCL_FALLBACK_RASTER 0x0001 /* rasterization */
#define RADEON_TCL_FALLBACK_UNFILLED 0x0002 /* unfilled tris */
#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x0004 /* twoside tris */
#define RADEON_TCL_FALLBACK_MATERIAL 0x0008 /* material in vb */
#define RADEON_TCL_FALLBACK_TEXGEN_0 0x0010 /* texgen, unit 0 */
#define RADEON_TCL_FALLBACK_TEXGEN_1 0x0020 /* texgen, unit 1 */
#define RADEON_TCL_FALLBACK_TEXGEN_2 0x0040 /* texgen, unit 2 */
#define RADEON_TCL_FALLBACK_TEXGEN_3 0x0080 /* texgen, unit 3 */
#define RADEON_TCL_FALLBACK_TEXGEN_4 0x0100 /* texgen, unit 4 */
#define RADEON_TCL_FALLBACK_TEXGEN_5 0x0200 /* texgen, unit 5 */
#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x0400 /* user disable */
#define RADEON_TCL_FALLBACK_BITMAP 0x0800 /* draw bitmap with points */
#define RADEON_TCL_FALLBACK_VERTEX_PROGRAM 0x1000 /* vertex program active */
#if R200_MERGED
#define TCL_FALLBACK( ctx, bit, mode ) radeonTclFallback( ctx, bit, mode )
#else
@ -88,33 +74,4 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
#endif
extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
int x, int y, int w, int h);
extern GLboolean radeonInitContext(radeonContextPtr radeon,
struct dd_function_table *functions,
const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate);
extern void radeonCleanupContext(radeonContextPtr radeon);
extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
__DRIdrawablePrivate * driDrawPriv,
__DRIdrawablePrivate * driReadPriv);
extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
/* ================================================================
* Debugging:
*/
#define DO_DEBUG 1
#if DO_DEBUG
extern int RADEON_DEBUG;
#else
#define RADEON_DEBUG 0
#endif
#define DEBUG_SYNC 0x1000
#define DEBUG_PIXEL 0x2000
#define DEBUG_MEMORY 0x4000
#endif /* __RADEON_CONTEXT_H__ */

69
src/mesa/drivers/dri/r300/radeon_ioctl.c
View file

@ -1,69 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#include <sched.h>
#include <errno.h>
#include "main/glheader.h"
#include "main/imports.h"
#include "main/macros.h"
#include "main/context.h"
#include "swrast/swrast.h"
#include "r300_context.h"
#include "radeon_ioctl.h"
#include "radeon_buffer.h"
#include "r300_ioctl.h"
#include "r300_state.h"
#include "radeon_reg.h"
#include "drirenderbuffer.h"
#include "vblank.h"
void radeonFlush(GLcontext * ctx)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
if (IS_R300_CLASS(radeon->radeonScreen))
r300Flush(ctx);
}
/* Make sure all commands have been sent to the hardware and have
* completed processing.
*/
void radeonFinish(GLcontext * ctx)
{
radeonFlush(ctx);
radeon_common_finish(ctx);
}

57
src/mesa/drivers/dri/r300/radeon_ioctl.h
View file

@ -1,57 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __RADEON_IOCTL_H__
#define __RADEON_IOCTL_H__
#include "main/simple_list.h"
#include "radeon_dri.h"
#include "radeon_lock.h"
#include "xf86drm.h"
#include "drm.h"
#if 0
#include "r200context.h"
#endif
#include "radeon_drm.h"
extern void radeonCopyBuffer(__DRIdrawablePrivate * drawable,
const drm_clip_rect_t * rect);
extern void radeonPageFlip(__DRIdrawablePrivate * drawable);
extern void radeonFlush(GLcontext * ctx);
extern void radeonFinish(GLcontext * ctx);
extern void radeonWaitForIdleLocked(radeonContextPtr radeon);
extern uint32_t radeonGetAge(radeonContextPtr radeon);
#endif /* __RADEON_IOCTL_H__ */

109
src/mesa/drivers/dri/r300/radeon_state.c
View file

@ -1,109 +0,0 @@
/**************************************************************************
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#include "main/glheader.h"
#include "main/imports.h"
#include "main/api_arrayelt.h"
#include "main/enums.h"
#include "main/framebuffer.h"
#include "main/colormac.h"
#include "main/light.h"
#include "swrast/swrast.h"
#include "vbo/vbo.h"
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
#include "r300_ioctl.h"
/* =============================================================
* Scissoring
*/
static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
{
if (ctx->Scissor.Enabled) {
/* We don't pipeline cliprect changes */
r300Flush(ctx);
radeonUpdateScissor(ctx);
}
}
/**
* Handle common enable bits.
* Called as a fallback by r200Enable/r300Enable.
*/
void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
switch(cap) {
case GL_SCISSOR_TEST:
/* We don't pipeline cliprect & scissor changes */
r300Flush(ctx);
radeon->state.scissor.enabled = state;
radeonUpdateScissor(ctx);
break;
default:
return;
}
}
/**
* Initialize default state.
* This function is called once at context init time from
* r200InitState/r300InitState
*/
void radeonInitState(radeonContextPtr radeon)
{
radeon->Fallback = 0;
}
/**
* Initialize common state functions.
* Called by r200InitStateFuncs/r300InitStateFuncs
*/
void radeonInitStateFuncs(struct dd_function_table *functions)
{
functions->Scissor = radeonScissor;
}

39
src/mesa/drivers/dri/r300/radeon_state.h
View file

@ -1,39 +0,0 @@
/*
Copyright (C) 2004 Nicolai Haehnle. All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __RADEON_STATE_H__
#define __RADEON_STATE_H__
extern void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state);
extern void radeonInitState(radeonContextPtr radeon);
extern void radeonInitStateFuncs(struct dd_function_table* functions);
#endif

14
src/mesa/drivers/dri/radeon/common_cmdbuf.h
View file

@ -1,10 +1,12 @@
#ifndef COMMON_CMDBUF_H
#define COMMON_CMDBUF_H
#include "radeon_cs.h"
void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller);
void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size);
void rcommonInitCmdBuf(radeonContextPtr rmesa);
void rcommonDestroyCmdBuf(radeonContextPtr rmesa);
void rcommonBeginBatch(radeonContextPtr rmesa,
@ -128,4 +130,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
/** Write a 32 bit float to the ring; requires 1 dword. */
#define OUT_BATCH_FLOAT32(f) \
OUT_BATCH(radeonPackFloat32((f)));
/* Fire the buffered vertices no matter what.
*/
static INLINE void radeon_firevertices(radeonContextPtr radeon)
{
if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
radeonFlush(radeon->glCtx);
}
#endif

27
src/mesa/drivers/dri/radeon/common_context.h
View file

@ -111,6 +111,13 @@ struct radeon_state_atom {
void (*emit) (GLcontext *, struct radeon_state_atom *atom);
};
struct radeon_hw_state {
/* Head of the linked list of state atoms. */
struct radeon_state_atom atomlist;
int max_state_size; /* Number of bytes necessary for a full state emit. */
GLboolean is_dirty, all_dirty;
};
/* Texture related */
typedef struct _radeon_texture_image radeon_texture_image;
@ -206,17 +213,6 @@ struct radeon_dma_buffer {
drmBufPtr buf;
};
/* A retained region, eg vertices for indexed vertices.
*/
struct radeon_dma_region {
struct radeon_dma_buffer *buf;
char *address; /* == buf->address */
int start, end, ptr; /* offsets from start of buf */
int aos_start;
int aos_stride;
int aos_size;
};
struct radeon_aos {
struct radeon_bo *bo; /** Buffer object where vertex data is stored */
int offset; /** Offset into buffer object, in bytes */
@ -388,6 +384,7 @@ struct radeon_context {
float initialMaxAnisotropy;
struct radeon_dma dma;
struct radeon_hw_state hw;
/* Rasterization and vertex state:
*/
GLuint TclFallback;
@ -434,13 +431,11 @@ struct radeon_context {
struct {
void (*get_lock)(radeonContextPtr radeon);
void (*update_viewport_offset)(GLcontext *ctx);
void (*flush)(GLcontext *ctx);
void (*set_all_dirty)(GLcontext *ctx);
void (*update_draw_buffer)(GLcontext *ctx);
void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
void (*emit_state)(radeonContextPtr rmesa);
void (*flush_vertices)(radeonContextPtr rmesa);
void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
void (*pre_emit_atoms)(radeonContextPtr rmesa);
void (*pre_emit_state)(radeonContextPtr rmesa);
} vtbl;
};
@ -502,4 +497,6 @@ extern int RADEON_DEBUG;
#define RADEON_DEBUG 0
#endif
#include "common_misc.h"
#include "common_cmdbuf.h"
#endif

155
src/mesa/drivers/dri/radeon/common_misc.c
View file

@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/colormac.h"
#include "main/light.h"
#include "main/framebuffer.h"
#include "main/simple_list.h"
#include "swrast/swrast.h"
#include "vbo/vbo.h"
@ -81,6 +82,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
int RADEON_DEBUG = (0);
#endif
#define DEBUG_CMDBUF 0
/* =============================================================
* Scissoring
*/
@ -215,6 +218,21 @@ void radeonUpdateScissor( GLcontext *ctx )
}
}
/* =============================================================
* Scissoring
*/
void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
if (ctx->Scissor.Enabled) {
/* We don't pipeline cliprect changes */
radeon_firevertices(radeon);
radeonUpdateScissor(ctx);
}
}
/* ================================================================
* SwapBuffers with client-side throttling
*/
@ -367,7 +385,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
}
rmesa->vtbl.flush(rmesa->glCtx);
radeon_firevertices(rmesa);
LOCK_HARDWARE( rmesa );
/* Throttle the frame rate -- only allow one pending swap buffers
@ -437,7 +455,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
}
rmesa->swap_ust = ust;
rmesa->vtbl.set_all_dirty(rmesa->glCtx);
rmesa->hw.all_dirty = GL_TRUE;
}
}
@ -465,7 +483,7 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
rmesa->sarea->pfCurrentPage);
}
rmesa->vtbl.flush(rmesa->glCtx);
radeon_firevertices(rmesa);
LOCK_HARDWARE( rmesa );
@ -516,16 +534,111 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
rmesa->vtbl.update_draw_buffer(rmesa->glCtx);
}
void radeonFlush(GLcontext *ctx)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
if (radeon->dma.flush)
radeon->dma.flush( ctx );
radeonEmitState(radeon);
if (radeon->cmdbuf.cs->cdw)
rcommonFlushCmdBuf(radeon, __FUNCTION__);
}
static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
{
BATCH_LOCALS(radeon);
struct radeon_state_atom *atom;
int dwords;
if (radeon->vtbl.pre_emit_atoms)
radeon->vtbl.pre_emit_atoms(radeon);
/* Emit actual atoms */
foreach(atom, &radeon->hw.atomlist) {
if ((atom->dirty || radeon->hw.all_dirty) == dirty) {
dwords = (*atom->check) (radeon->glCtx, atom);
if (dwords) {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
radeon_print_state_atom(atom);
}
if (atom->emit) {
(*atom->emit)(radeon->glCtx, atom);
} else {
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
}
atom->dirty = GL_FALSE;
} else {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
fprintf(stderr, " skip state %s\n",
atom->name);
}
}
}
}
COMMIT_BATCH();
}
void radeonEmitState(radeonContextPtr radeon)
{
if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
fprintf(stderr, "%s\n", __FUNCTION__);
if (radeon->vtbl.pre_emit_state)
radeon->vtbl.pre_emit_state(radeon);
/* this code used to return here but now it emits zbs */
if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
return;
/* To avoid going across the entire set of states multiple times, just check
* for enough space for the case of emitting all state, and inline the
* radeonAllocCmdBuf code here without all the checks.
*/
rcommonEnsureCmdBufSpace(radeon, radeon->hw.max_state_size, __FUNCTION__);
/* We always always emit zbs, this is due to a bug found by keithw in
the hardware and rediscovered after Erics changes by me.
if you ever touch this code make sure you emit zbs otherwise
you get tcl lockups on at least M7/7500 class of chips - airlied */
/* special r100 case */
// rmesa->hw.zbs.dirty=1;
if (!radeon->cmdbuf.cs->cdw) {
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin reemit state\n");
radeonEmitAtoms(radeon, GL_FALSE);
}
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin dirty state\n");
radeonEmitAtoms(radeon, GL_TRUE);
radeon->hw.is_dirty = GL_FALSE;
radeon->hw.all_dirty = GL_FALSE;
}
/* Make sure all commands have been sent to the hardware and have
* completed processing.
*/
void radeon_common_finish(GLcontext * ctx)
void radeonFinish(GLcontext * ctx)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
int i;
radeonFlush(ctx);
if (radeon->radeonScreen->kernel_mm) {
for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
struct radeon_renderbuffer *rrb;
@ -611,7 +724,7 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller)
rmesa->cmdbuf.flushing = 1;
if (rmesa->cmdbuf.cs->cdw) {
ret = radeon_cs_emit(rmesa->cmdbuf.cs);
rmesa->vtbl.set_all_dirty(rmesa->glCtx);
rmesa->hw.all_dirty = GL_TRUE;
}
radeon_cs_erase(rmesa->cmdbuf.cs);
rmesa->cmdbuf.flushing = 0;
@ -650,20 +763,18 @@ void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *ca
}
}
void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size)
void rcommonInitCmdBuf(radeonContextPtr rmesa)
{
GLuint size;
/* Initialize command buffer */
size = 256 * driQueryOptioni(&rmesa->optionCache,
"command_buffer_size");
if (size < 2 * max_state_size) {
size = 2 * max_state_size + 65535;
if (size < 2 * rmesa->hw.max_state_size) {
size = 2 * rmesa->hw.max_state_size + 65535;
}
if (size > 64 * 256)
size = 64 * 256;
size = 64 * 1024 / 4;
if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) {
fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n",
sizeof(drm_r300_cmd_header_t));
@ -671,7 +782,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size)
sizeof(drm_radeon_cmd_buffer_t));
fprintf(stderr,
"Allocating %d bytes command buffer (max state is %d bytes)\n",
size * 4, max_state_size * 4);
size * 4, rmesa->hw.max_state_size * 4);
}
if (rmesa->radeonScreen->kernel_mm) {
@ -725,7 +836,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
if (!rmesa->cmdbuf.cs->cdw && dostate) {
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "Reemit state after flush (from %s)\n", function);
rmesa->vtbl.emit_state(rmesa);
radeonEmitState(rmesa);
}
radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line);
}
@ -927,6 +1038,20 @@ void radeonCleanupContext(radeonContextPtr radeon)
}
}
/* Force the context `c' to be unbound from its buffer.
*/
GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
{
radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
radeon->glCtx);
return GL_TRUE;
}
static void
radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
GLframebuffer *draw)
@ -1810,7 +1935,7 @@ static void radeon_teximage(
radeonTexObj* t = radeon_tex_obj(texObj);
radeon_texture_image* image = get_radeon_texture_image(texImage);
rmesa->vtbl.flush_vertices(rmesa);
radeon_firevertices(rmesa);
t->validated = GL_FALSE;
@ -1968,7 +2093,7 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level,
radeonTexObj* t = radeon_tex_obj(texObj);
radeon_texture_image* image = get_radeon_texture_image(texImage);
rmesa->vtbl.flush_vertices(rmesa);
radeon_firevertices(rmesa);
t->validated = GL_FALSE;
pixels = _mesa_validate_pbo_teximage(ctx, dims,
@ -2373,7 +2498,7 @@ void radeonSpanRenderStart(GLcontext * ctx)
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
int i;
rmesa->vtbl.flush_vertices(rmesa);
radeon_firevertices(rmesa);
for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled)

5
src/mesa/drivers/dri/radeon/common_misc.h
View file

@ -6,6 +6,7 @@
void radeonRecalcScissorRects(radeonContextPtr radeon);
void radeonSetCliprects(radeonContextPtr radeon);
void radeonUpdateScissor( GLcontext *ctx );
void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h);
void radeonWaitForIdleLocked(radeonContextPtr radeon);
extern uint32_t radeonGetAge(radeonContextPtr radeon);
@ -26,6 +27,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
void *sharedContextPrivate);
void radeonCleanupContext(radeonContextPtr radeon);
GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
__DRIdrawablePrivate * driDrawPriv,
@ -132,6 +134,9 @@ void rcommon_flush_last_swtcl_prim(GLcontext *ctx);
void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize);
void radeonFlush(GLcontext *ctx);
void radeonFinish(GLcontext * ctx);
void radeonEmitState(radeonContextPtr radeon);
static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa)
{

46
src/mesa/drivers/dri/radeon/radeon_context.c
View file

@ -215,29 +215,17 @@ static void r100_get_lock(radeonContextPtr radeon)
}
}
static void r100_vtbl_flush(GLcontext *ctx)
{
RADEON_FIREVERTICES(R100_CONTEXT(ctx));
}
static void r100_vtbl_set_all_dirty(GLcontext *ctx)
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
rmesa->hw.all_dirty = GL_TRUE;
}
static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
}
static void r100_vtbl_emit_state(radeonContextPtr rmesa)
static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
{
radeonEmitState((r100ContextPtr)rmesa);
}
static void r100_vtbl_flush_vertices(radeonContextPtr rmesa)
{
RADEON_FIREVERTICES(((r100ContextPtr)rmesa));
r100ContextPtr rmesa = (r100ContextPtr)radeon;
/* r100 always needs to emit ZBS to avoid TCL lockups */
rmesa->hw.zbs.dirty = 1;
radeon->hw.is_dirty = 1;
}
@ -245,13 +233,10 @@ static void r100_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r100_get_lock;
radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
radeon->vtbl.flush = r100_vtbl_flush;
radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty;
radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer;
radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
radeon->vtbl.emit_state = r100_vtbl_emit_state;
radeon->vtbl.swtcl_flush = r100_swtcl_flush;
radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices;
radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
}
/* Create the device specific context.
@ -344,7 +329,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->hw.all_dirty = GL_TRUE;
rmesa->radeon.hw.all_dirty = GL_TRUE;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
@ -503,7 +488,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
/* check if we're deleting the currently bound context */
if (rmesa == current) {
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
_mesa_make_current(NULL, NULL, NULL);
}
@ -553,16 +538,3 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
}
}
/* Force the context `c' to be unbound from its buffer.
*/
GLboolean
radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
{
r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx);
return GL_TRUE;
}

24
src/mesa/drivers/dri/radeon/radeon_context.h
View file

@ -296,10 +296,7 @@ struct radeon_texture_state {
#define SHN_SHININESS 1
#define SHN_STATE_SIZE 2
struct radeon_hw_state {
/* Head of the linked list of state atoms. */
struct radeon_state_atom atomlist;
struct r100_hw_state {
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
* - eliding noop statechange loops? (except line stipple count)
@ -324,8 +321,6 @@ struct radeon_hw_state {
struct radeon_state_atom glt;
struct radeon_state_atom txr[3]; /* for NPOT */
int max_state_size; /* Number of bytes necessary for a full state emit. */
GLboolean is_dirty, all_dirty;
};
@ -354,14 +349,6 @@ struct radeon_tcl_info {
struct radeon_bo *indexed_bo;
// struct radeon_dma_region indexed_verts;
struct radeon_dma_region obj;
struct radeon_dma_region rgba;
struct radeon_dma_region spec;
struct radeon_dma_region fog;
struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
struct radeon_dma_region norm;
int elt_cmd_offset; /** Offset into the cmdbuf */
int elt_cmd_start;
int elt_used;
@ -391,8 +378,6 @@ struct r100_swtcl_info {
GLuint specoffset;
GLboolean needproj;
struct radeon_dma_region indexed_verts;
};
@ -411,17 +396,13 @@ struct r100_context {
/* Driver and hardware state management
*/
struct radeon_hw_state hw;
struct r100_hw_state hw;
struct r100_state state;
/* Vertex buffers
*/
struct radeon_ioctl ioctl;
struct radeon_store store;
/* A full state emit as of the first state emit in the main store, in case
* the context is lost.
*/
struct radeon_store backup_store;
/* TCL stuff
*/
@ -455,7 +436,6 @@ struct r100_context {
GLuint c_textureBytes;
GLuint c_vertexBuffers;
GLboolean save_on_next_emit;
};
#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx))

202
src/mesa/drivers/dri/radeon/radeon_ioctl.c
View file

@ -59,60 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RADEON_TIMEOUT 512
#define RADEON_IDLE_RETRY 16
#define DEBUG_CMDBUF 1
static void radeonSaveHwState( r100ContextPtr rmesa )
{
struct radeon_state_atom *atom;
char * dest = rmesa->backup_store.cmd_buf;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s\n", __FUNCTION__);
rmesa->backup_store.cmd_used = 0;
foreach( atom, &rmesa->hw.atomlist ) {
if ( atom->check( rmesa->radeon.glCtx, 0 ) ) {
int size = atom->cmd_size * 4;
memcpy( dest, atom->cmd, size);
dest += size;
rmesa->backup_store.cmd_used += size;
if (RADEON_DEBUG & DEBUG_STATE)
radeon_print_state_atom( atom );
}
}
assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ );
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Returning to radeonEmitState\n");
}
/* At this point we were in FlushCmdBufLocked but we had lost our context, so
* we need to unwire our current cmdbuf, hook the one with the saved state in
* it, flush it, and then put the current one back. This is so commands at the
* start of a cmdbuf can rely on the state being kept from the previous one.
*/
static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa )
{
GLuint nr_released_bufs;
struct radeon_store saved_store;
if (rmesa->backup_store.cmd_used == 0)
return;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Emitting backup state on lost context\n");
rmesa->radeon.lost_context = GL_FALSE;
nr_released_bufs = rmesa->radeon.dma.nr_released_bufs;
saved_store = rmesa->store;
rmesa->radeon.dma.nr_released_bufs = 0;
rmesa->store = rmesa->backup_store;
rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
rmesa->radeon.dma.nr_released_bufs = nr_released_bufs;
rmesa->store = saved_store;
}
/* =============================================================
* Kernel command buffer handling
@ -125,107 +71,33 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
{
int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
make_empty_list(&rmesa->hw.atomlist);
rmesa->hw.atomlist.name = "atom-list";
make_empty_list(&rmesa->radeon.hw.atomlist);
rmesa->radeon.hw.atomlist.name = "atom-list";
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc);
for (i = 0; i < mtu; ++i) {
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.cube[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]);
}
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl);
for (i = 0; i < 3 + mtu; ++i)
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]);
for (i = 0; i < 8; ++i)
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
for (i = 0; i < 6; ++i)
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog);
insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt);
}
static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty)
{
BATCH_LOCALS(&r100->radeon);
struct radeon_state_atom *atom;
int dwords;
/* Emit actual atoms */
foreach(atom, &r100->hw.atomlist) {
if ((atom->dirty || r100->hw.all_dirty) == dirty) {
dwords = (*atom->check) (r100->radeon.glCtx, atom);
if (dwords) {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
radeon_print_state_atom(atom);
}
if (atom->emit) {
(*atom->emit)(r100->radeon.glCtx, atom);
} else {
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
}
atom->dirty = GL_FALSE;
} else {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
fprintf(stderr, " skip state %s\n",
atom->name);
}
}
}
}
COMMIT_BATCH();
}
void radeonEmitState( r100ContextPtr rmesa )
{
if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
fprintf(stderr, "%s\n", __FUNCTION__);
if (rmesa->save_on_next_emit) {
radeonSaveHwState(rmesa);
rmesa->save_on_next_emit = GL_FALSE;
}
/* this code used to return here but now it emits zbs */
/* To avoid going across the entire set of states multiple times, just check
* for enough space for the case of emitting all state, and inline the
* radeonAllocCmdBuf code here without all the checks.
*/
rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__);
/* We always always emit zbs, this is due to a bug found by keithw in
the hardware and rediscovered after Erics changes by me.
if you ever touch this code make sure you emit zbs otherwise
you get tcl lockups on at least M7/7500 class of chips - airlied */
rmesa->hw.zbs.dirty=1;
if (!rmesa->radeon.cmdbuf.cs->cdw) {
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin reemit state\n");
radeonEmitAtoms(rmesa, GL_FALSE);
}
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "Begin dirty state\n");
radeonEmitAtoms(rmesa, GL_TRUE);
rmesa->hw.is_dirty = GL_FALSE;
rmesa->hw.all_dirty = GL_FALSE;
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
}
/* Fire a section of the retained (indexed_verts) buffer as a regular
@ -240,7 +112,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
radeonEmitState( rmesa );
radeonEmitState(&rmesa->radeon);
#if RADEON_OLD_PACKETS
BEGIN_BATCH(8);
@ -318,7 +190,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
radeonEmitState( rmesa );
radeonEmitState(&rmesa->radeon);
rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
@ -679,35 +551,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
}
UNLOCK_HARDWARE( &rmesa->radeon );
rmesa->hw.all_dirty = GL_TRUE;
rmesa->radeon.hw.all_dirty = GL_TRUE;
}
void radeonFlush( GLcontext *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
if (rmesa->radeon.dma.flush)
rmesa->radeon.dma.flush( ctx );
radeonEmitState( rmesa );
if (rmesa->radeon.cmdbuf.cs->cdw)
rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
}
/* Make sure all commands have been sent to the hardware and have
* completed processing.
*/
void radeonFinish( GLcontext *ctx )
{
radeonFlush( ctx );
radeon_common_finish(ctx);
}
void radeonInitIoctlFuncs( GLcontext *ctx )
{
ctx->Driver.Clear = radeonClear;

14
src/mesa/drivers/dri/radeon/radeon_ioctl.h
View file

@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "radeon_lock.h"
#include "radeon_cs_legacy.h"
extern void radeonEmitState( r100ContextPtr rmesa );
extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
GLuint vertex_size,
struct radeon_bo *bo,
@ -104,7 +103,7 @@ do { \
do { \
RADEON_NEWPRIM( rmesa ); \
rmesa->hw.ATOM.dirty = GL_TRUE; \
rmesa->hw.is_dirty = GL_TRUE; \
rmesa->radeon.hw.is_dirty = GL_TRUE; \
} while (0)
#define RADEON_DB_STATE( ATOM ) \
@ -118,7 +117,7 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa,
GLuint *tmp;
RADEON_NEWPRIM( rmesa );
atom->dirty = GL_TRUE;
rmesa->hw.is_dirty = GL_TRUE;
rmesa->radeon.hw.is_dirty = GL_TRUE;
tmp = atom->cmd;
atom->cmd = atom->lastcmd;
atom->lastcmd = tmp;
@ -128,15 +127,6 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa,
return 0;
}
/* Fire the buffered vertices no matter what.
*/
#define RADEON_FIREVERTICES( rmesa ) \
do { \
if (rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \
radeonFlush( rmesa->radeon.glCtx ); \
} \
} while (0)
/* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
* are available, you will also be adding an rmesa->state.max_state_size because
* r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.

2
src/mesa/drivers/dri/radeon/radeon_screen.c
View file

@ -1523,7 +1523,7 @@ const struct __DriverAPIRec driDriverAPI = {
.DestroyBuffer = radeonDestroyBuffer,
.SwapBuffers = radeonSwapBuffers,
.MakeCurrent = radeonMakeCurrent,
.UnbindContext = r200UnbindContext,
.UnbindContext = radeonUnbindContext,
.GetSwapInfo = getSwapInfo,
.GetDrawableMSC = driDrawableGetMSC32,
.WaitForMSC = driWaitForMSC32,

26
src/mesa/drivers/dri/radeon/radeon_state.c
View file

@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "swrast_setup/swrast_setup.h"
#include "radeon_context.h"
#include "common_cmdbuf.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
#include "radeon_tcl.h"
@ -406,23 +407,6 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
}
}
/* =============================================================
* Scissoring
*/
static void radeonScissor( GLcontext *ctx,
GLint x, GLint y, GLsizei w, GLsizei h )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
if ( ctx->Scissor.Enabled ) {
RADEON_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */
radeonUpdateScissor( ctx );
}
}
/* =============================================================
* Culling
*/
@ -567,7 +551,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
/* TODO: push this into cmd mechanism
*/
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
LOCK_HARDWARE( &rmesa->radeon );
/* FIXME: Use window x,y offsets into stipple RAM.
@ -1415,7 +1399,7 @@ void radeonUpdateWindow( GLcontext *ctx )
float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
RADEON_STATECHANGE( rmesa, vpt );
rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
@ -1561,7 +1545,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
fprintf(stderr, "%s %s\n", __FUNCTION__,
_mesa_lookup_enum_by_nr( mode ));
RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */
if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
/* 0 (GL_NONE) buffers or multiple color drawing buffers */
@ -1843,7 +1827,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
}
case GL_SCISSOR_TEST:
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
rmesa->radeon.state.scissor.enabled = state;
radeonUpdateScissor( ctx );
break;

12
src/mesa/drivers/dri/radeon/radeon_state_init.c
View file

@ -171,8 +171,8 @@ void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
fprintf(stderr, msg);
fprintf(stderr, ": ");
foreach(l, &rmesa->hw.atomlist) {
if (l->dirty || rmesa->hw.all_dirty)
foreach(l, &rmesa->radeon.hw.atomlist) {
if (l->dirty || rmesa->radeon.hw.all_dirty)
fprintf(stderr, "%s, ", l->name);
}
@ -512,7 +512,7 @@ void radeonInitState( r100ContextPtr rmesa )
drawPitch = rmesa->radeon.radeonScreen->frontPitch;
}
rmesa->hw.max_state_size = 0;
rmesa->radeon.hw.max_state_size = 0;
#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
do { \
@ -524,7 +524,7 @@ void radeonInitState( r100ContextPtr rmesa )
rmesa->hw.ATOM.check = check_##CHK; \
rmesa->hw.ATOM.dirty = GL_TRUE; \
rmesa->hw.ATOM.idx = IDX; \
rmesa->hw.max_state_size += SZ * sizeof(int); \
rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
} while (0)
#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
@ -932,7 +932,7 @@ void radeonInitState( r100ContextPtr rmesa )
rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
rmesa->hw.all_dirty = GL_TRUE;
rmesa->radeon.hw.all_dirty = GL_TRUE;
rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
rcommonInitCmdBuf(&rmesa->radeon);
}

12
src/mesa/drivers/dri/radeon/radeon_swtcl.c
View file

@ -285,11 +285,11 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
r100ContextPtr rmesa = R100_CONTEXT(ctx);
rcommonEnsureCmdBufSpace(&rmesa->radeon,
rmesa->hw.max_state_size + (12*sizeof(int)),
rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
__FUNCTION__);
radeonEmitState(rmesa);
radeonEmitState(&rmesa->radeon);
radeonEmitVertexAOS( rmesa,
rmesa->radeon.swtcl.vertex_size,
rmesa->radeon.dma.current,
@ -372,9 +372,6 @@ static GLboolean radeon_run_render( GLcontext *ctx,
tnl_render_func *tab = TAG(render_tab_verts);
GLuint i;
if (rmesa->swtcl.indexed_verts.buf)
RELEASE_ELT_VERTS();
if (rmesa->radeon.swtcl.RenderIndex != 0 ||
!radeon_dma_validate_render( ctx, VB ))
return GL_TRUE;
@ -750,7 +747,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
if (mode) {
rmesa->radeon.Fallback |= bit;
if (oldfallback == 0) {
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
_swsetup_Wakeup( ctx );
rmesa->radeon.swtcl.RenderIndex = ~0;
@ -831,7 +828,4 @@ void radeonDestroySwtcl( GLcontext *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
// if (rmesa->swtcl.indexed_verts.buf)
// radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
// __FUNCTION__ );
}

8
src/mesa/drivers/dri/radeon/radeon_tcl.c
View file

@ -126,7 +126,7 @@ static GLboolean discrete_prim[0x10] = {
#define RESET_STIPPLE() do { \
RADEON_STATECHANGE( rmesa, lin ); \
radeonEmitState( rmesa ); \
radeonEmitState(&rmesa->radeon); \
} while (0)
#define AUTO_STIPPLE( mode ) do { \
@ -137,7 +137,7 @@ static GLboolean discrete_prim[0x10] = {
else \
rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
~RADEON_LINE_PATTERN_AUTO_RESET; \
radeonEmitState( rmesa ); \
radeonEmitState(&rmesa->radeon); \
} while (0)
@ -149,7 +149,7 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
if (rmesa->radeon.dma.flush)
rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + ELTS_BUFSZ(nr) +
rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) +
AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
radeonEmitAOS( rmesa,
@ -178,7 +178,7 @@ static void radeonEmitPrim( GLcontext *ctx,
rcommonEnsureCmdBufSpace( &rmesa->radeon,
AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
radeonEmitAOS( rmesa,
rmesa->tcl.nr_aos_components,

2
src/mesa/drivers/dri/radeon/radeon_tex.c
View file

@ -381,7 +381,7 @@ static void radeonDeleteTexture( GLcontext *ctx,
}
if ( rmesa ) {
RADEON_FIREVERTICES( rmesa );
radeon_firevertices(&rmesa->radeon);
for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
if ( t == rmesa->state.texture.unit[i].texobj ) {
rmesa->state.texture.unit[i].texobj = NULL;