From 1053a5bb925a21606cdd9d72e9c899443d87a0b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 7 May 2026 18:38:11 -0400 Subject: [PATCH] amd/tools: rewrite ac_print_tiling_layouts to print all layouts, including XORs Instead of expecting just 1 address bit to be flipped by 1 coordinate bit, expect any address bits to be flipped by 1 coordinate bit. If multiple coordinate bits flip the same address bit, that means all those coordinate bits are XOR'd. --- .../common/tools/ac_print_tiling_layouts.c | 112 ++++++++++-------- 1 file changed, 61 insertions(+), 51 deletions(-) diff --git a/src/amd/common/tools/ac_print_tiling_layouts.c b/src/amd/common/tools/ac_print_tiling_layouts.c index fb04e088b15..752b06f9549 100644 --- a/src/amd/common/tools/ac_print_tiling_layouts.c +++ b/src/amd/common/tools/ac_print_tiling_layouts.c @@ -97,7 +97,7 @@ addrlib_create(const struct amdgpu_device *dev) return lib.hLib; } -#define DIPLAYABLE BITFIELD_BIT(5) +#define DISPLAYABLE BITFIELD_BIT(5) typedef struct { unsigned tile_mode_index; @@ -179,8 +179,8 @@ get_tile_size(ADDR_HANDLE hlib, unsigned gfx_version, unsigned bpp, unsigned swi *tile_height = out.blockHeight; assert(out.blockSlices == 1); } else { - AddrTileMode mode = swizzle_mode & ~DIPLAYABLE; - bool display = !!(swizzle_mode & DIPLAYABLE); + AddrTileMode mode = swizzle_mode & ~DISPLAYABLE; + bool display = !!(swizzle_mode & DISPLAYABLE); ADDR_TILEINFO tile_info = {0}; ADDR_COMPUTE_SURFACE_INFO_INPUT in = { .size = sizeof(in), @@ -195,8 +195,7 @@ get_tile_size(ADDR_HANDLE hlib, unsigned gfx_version, unsigned bpp, unsigned swi .flags = { .color = 1, .display = display, - .prt = mode == ADDR_TM_PRT_TILED_THIN1 || - mode == ADDR_TM_PRT_2D_TILED_THIN1, + .prt = mode == ADDR_TM_PRT_TILED_THIN1, }, .numFrags = 1, .tileType = display ? ADDR_DISPLAYABLE : ADDR_NON_DISPLAYABLE, @@ -308,26 +307,30 @@ print_tiling_layouts(const struct amdgpu_device *dev) static const unsigned gfx6_array_modes_2D[] = { ADDR_TM_LINEAR_ALIGNED, ADDR_TM_1D_TILED_THIN1, - ADDR_TM_1D_TILED_THIN1 | DIPLAYABLE, -#if 0 /* Layouts with XORs are commented out for now. */ + ADDR_TM_1D_TILED_THIN1 | DISPLAYABLE, ADDR_TM_2D_TILED_THIN1, - ADDR_TM_2D_TILED_THIN1 | DIPLAYABLE, + ADDR_TM_2D_TILED_THIN1 | DISPLAYABLE, + }; + static const unsigned gfx7_array_modes_2D[] = { + ADDR_TM_LINEAR_ALIGNED, + ADDR_TM_1D_TILED_THIN1, + ADDR_TM_1D_TILED_THIN1 | DISPLAYABLE, + ADDR_TM_2D_TILED_THIN1, + ADDR_TM_2D_TILED_THIN1 | DISPLAYABLE, ADDR_TM_PRT_TILED_THIN1, -#endif - /* ADDR_TM_PRT_2D_TILED_THIN1 is not supported by gfx7-8 */ }; /* Note: Layouts with XORs are commented out for now. */ - static const unsigned gfx9_swizzle_mode_2D[] = { - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, /*16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,*/ + static const unsigned gfx9_swizzle_modes_2D[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, }; - static const unsigned gfx10_swizzle_mode_2D[] = { - 0, 1, 2, 5, 6, 9, 10, /*17, 18, 21, 22, 23, 24, 25, 26, 27*/ + static const unsigned gfx10_swizzle_modes_2D[] = { + 0, 1, 2, 5, 6, 9, 10, 17, 18, 21, 22, 24, 25, 26, 27, }; - static const unsigned gfx11_swizzle_mode_2D[] = { - 0, 2, 6, 10, /*18, 21, 22, 24, 25, 26, 27, 28, 29, 30, 31*/ + static const unsigned gfx11_swizzle_modes_2D[] = { + 0, 2, 6, 10, 18, 22, 24, 26, 27, 28, 30, 31, }; static const unsigned gfx12_swizzle_modes_2D[] = { - 0, 1, 2, 3, 4 + 0, 1, 2, 3, 4, }; const unsigned *swizzle_modes_2D = NULL; unsigned num_swizzle_modes_2D = 0; @@ -336,14 +339,17 @@ print_tiling_layouts(const struct amdgpu_device *dev) swizzle_modes_2D = gfx12_swizzle_modes_2D; num_swizzle_modes_2D = ARRAY_SIZE(gfx12_swizzle_modes_2D); } else if (gfx_version >= 11) { - swizzle_modes_2D = gfx11_swizzle_mode_2D; - num_swizzle_modes_2D = ARRAY_SIZE(gfx11_swizzle_mode_2D); + swizzle_modes_2D = gfx11_swizzle_modes_2D; + num_swizzle_modes_2D = ARRAY_SIZE(gfx11_swizzle_modes_2D); } else if (gfx_version >= 10) { - swizzle_modes_2D = gfx10_swizzle_mode_2D; - num_swizzle_modes_2D = ARRAY_SIZE(gfx10_swizzle_mode_2D); + swizzle_modes_2D = gfx10_swizzle_modes_2D; + num_swizzle_modes_2D = ARRAY_SIZE(gfx10_swizzle_modes_2D); } else if (gfx_version >= 9) { - swizzle_modes_2D = gfx9_swizzle_mode_2D; - num_swizzle_modes_2D = ARRAY_SIZE(gfx9_swizzle_mode_2D); + swizzle_modes_2D = gfx9_swizzle_modes_2D; + num_swizzle_modes_2D = ARRAY_SIZE(gfx9_swizzle_modes_2D); + } else if (gfx_version >= 7) { + swizzle_modes_2D = gfx7_array_modes_2D; + num_swizzle_modes_2D = ARRAY_SIZE(gfx7_array_modes_2D); } else { swizzle_modes_2D = gfx6_array_modes_2D; num_swizzle_modes_2D = ARRAY_SIZE(gfx6_array_modes_2D); @@ -359,45 +365,49 @@ print_tiling_layouts(const struct amdgpu_device *dev) unsigned num_x_bits = util_logbase2(tile_width); unsigned num_y_bits = util_logbase2(tile_height); + unsigned num_addr_bits = util_logbase2(bpp / 8) + num_x_bits + num_y_bits; - ADDR_EQUATION equation = { - .numBits = util_logbase2(bpp / 8) + num_x_bits + num_y_bits, - .numBitComponents = 1, - }; + /* Precompute which address bits are flipped by each coordinate bit. */ + uint32_t coord_bit_flips_addr_bits[2][32] = {0}; + + assert(num_x_bits < 32 && num_y_bits < 32); for (unsigned coord = 0; coord < 2; coord++) { - for (unsigned bit = 0; bit < (coord ? num_y_bits : num_x_bits); bit++) { - unsigned x = coord == 0 ? BITFIELD_BIT(bit) : 0; - unsigned y = coord == 1 ? BITFIELD_BIT(bit) : 0; - unsigned addr = addr_from_coord(lib, gfx_version, &legacy_info, bpp, swizzle_mode, x, y); - unsigned addr_pos = u_bit_scan(&addr); - assert(addr == 0 && "layout with XORs are unhandled"); -#if 0 - printf("bpp %u, sw %u, %cbit %u (%u,%u), pos %u\n", bpp, swizzle_mode, "xy"[coord], bit, x, y, bit_pos); -#endif - assert(addr_pos < equation.numBits); - assert(!equation.addr[addr_pos].valid); + for (unsigned coord_bit = 0; coord_bit < (coord ? num_y_bits : num_x_bits); coord_bit++) { + unsigned x = coord == 0 ? BITFIELD_BIT(coord_bit) : 0; + unsigned y = coord == 1 ? BITFIELD_BIT(coord_bit) : 0; - equation.addr[addr_pos].valid = true; - equation.addr[addr_pos].channel = coord; - equation.addr[addr_pos].index = bit; + coord_bit_flips_addr_bits[coord][coord_bit] = + addr_from_coord(lib, gfx_version, &legacy_info, bpp, swizzle_mode, x, y); } } - /* Print the equation. */ - printf("%s, bpe %u, sw %2u, {", dev->name, bpp / 8, swizzle_mode); - for (unsigned bit = 0; bit < equation.numBits; bit++) { - for (unsigned comp = 0; comp < equation.numBitComponents; comp++) { - ADDR_CHANNEL_SETTING swizzle = equation.comps[comp][bit]; + /* Print inputs. */ + if (gfx_version >= 9) { + printf("%-17s, bpe %u, sw %2u, {", dev->name, bpp / 8, swizzle_mode); + } else { + printf("%-17s, bpe %u, sw %s%u, {", dev->name, bpp / 8, + swizzle_mode & DISPLAYABLE ? "D" : (swizzle_mode < 10 ? " " : ""), + swizzle_mode & (DISPLAYABLE - 1)); + } - if (swizzle.valid) { - printf("%c%u", "XYZS"[swizzle.channel], swizzle.index); - } else { - printf(" 0"); + /* Print the layout. */ + for (unsigned addr_bit = 0; addr_bit < num_addr_bits; addr_bit++) { + bool found = false; /* multiple matches are XOR'd */ + + for (unsigned coord = 0; coord < 2; coord++) { + for (unsigned coord_bit = 0; coord_bit < (coord ? num_y_bits : num_x_bits); coord_bit++) { + if (coord_bit_flips_addr_bits[coord][coord_bit] & BITFIELD_BIT(addr_bit)) { + printf("%s%c%u", found ? "^" : "", "XYZS"[coord], coord_bit); + found = true; + } } } - if (bit < equation.numBits - 1) + if (!found) + printf("0"); + + if (addr_bit < num_addr_bits - 1) printf(", "); } printf("}\n");