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radeon: tiling support

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This commit is contained in:
Dave Airlie 2009-04-02 13:35:09 +10:00
parent 617c5262c6
commit 104d542205
2 changed files with 4 additions and 4 deletions
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6
src/mesa/drivers/dri/r300/r300_cmdbuf.c
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@ -230,11 +230,11 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
cbpitch |= R300_COLOR_TILE_ENABLE;
BEGIN_BATCH_NO_AUTOSTATE(6);
BEGIN_BATCH_NO_AUTOSTATE(8);
OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
OUT_BATCH(cbpitch);
OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}
@ -282,7 +282,7 @@ static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom
}
OUT_BATCH(atom->cmd[0]);
atom->cmd[1] &= ~(3 << 0);
atom->cmd[1] &= ~0xf;
atom->cmd[1] |= format;
OUT_BATCH(atom->cmd[1]);
OUT_BATCH(atom->cmd[2]);

2
src/mesa/drivers/dri/r300/r300_ioctl.c
View file

@ -624,7 +624,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
/* HW depth */
if (mask & BUFFER_BIT_DEPTH) {
tri_mask |= BUFFER_BIT_DEPTH;
tri_mask |= BUFFER_BIT_DEPTH;
}
/* If we're doing a tri pass for depth/stencil, include a likely color