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nir_to_tgsi: Use nir_opt_offsets for load_ubo_vec4.

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This helps non-native-integers hardware where relative addressing of UBOs
has a constant offset field, and having addressing math (particularly for
D3D9) emitted as ALU ops ends up running us out of constants.  For
native-integers drivers (such as softpipe), the possible-overflow check
typically triggers and we end up not folding.

r300:
total instructions in shared programs: 1279167 -> 1278731 (-0.03%)
instructions in affected programs: 50834 -> 50398 (-0.86%)
total temps in shared programs: 213736 -> 213687 (-0.02%)
temps in affected programs: 598 -> 549 (-8.19%)
total consts in shared programs: 952973 -> 952850 (-0.01%)
consts in affected programs: 26776 -> 26653 (-0.46%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14309>
This commit is contained in:
Emma Anholt 2021-12-26 09:07:32 -08:00 • committed by Marge Bot
parent 645ca56425
commit 1048e6113e
1 changed files with 15 additions and 0 deletions
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15
src/gallium/auxiliary/nir/nir_to_tgsi.c
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@ -2573,6 +2573,21 @@ ntt_optimize_nir(struct nir_shader *s, struct pipe_screen *screen)
NIR_PASS(progress, s, nir_opt_undef);
NIR_PASS(progress, s, nir_opt_loop_unroll);
/* Try to fold addressing math into ubo_vec4's base to avoid load_consts
* and ALU ops for it.
*/
static const nir_opt_offsets_options offset_options = {
.ubo_vec4_max = ~0,
/* No const offset in TGSI for shared accesses. */
.shared_max = 0,
/* unused intrinsics */
.uniform_max = 0,
.buffer_max = 0,
};
NIR_PASS(progress, s, nir_opt_offsets, &offset_options);
} while (progress);
}