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intel/brw: Stop using namespace for brw_builder

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33076>
This commit is contained in:
Caio Oliveira 2024-12-29 16:06:27 -08:00 • committed by Marge Bot
parent 5ac82efd35
commit 1043187ec6
5 changed files with 812 additions and 816 deletions
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1594
src/intel/compiler/brw_builder.h
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File diff suppressed because it is too large Load diff

8
src/intel/compiler/brw_fs.cpp
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@ -1602,7 +1602,7 @@ bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag)
namespace brw {
brw_reg
fetch_payload_reg(const brw::brw_builder &bld, uint8_t regs[2],
fetch_payload_reg(const brw_builder &bld, uint8_t regs[2],
brw_reg_type type, unsigned n)
{
if (!regs[0])
@ -1610,7 +1610,7 @@ namespace brw {
if (bld.dispatch_width() > 16) {
const brw_reg tmp = bld.vgrf(type, n);
const brw::brw_builder hbld = bld.exec_all().group(16, 0);
const brw_builder hbld = bld.exec_all().group(16, 0);
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
brw_reg *const components = new brw_reg[m * n];
@ -1631,7 +1631,7 @@ namespace brw {
}
brw_reg
fetch_barycentric_reg(const brw::brw_builder &bld, uint8_t regs[2])
fetch_barycentric_reg(const brw_builder &bld, uint8_t regs[2])
{
if (!regs[0])
return brw_reg();
@ -1639,7 +1639,7 @@ namespace brw {
return fetch_payload_reg(bld, regs, BRW_TYPE_F, 2);
const brw_reg tmp = bld.vgrf(BRW_TYPE_F, 2);
const brw::brw_builder hbld = bld.exec_all().group(8, 0);
const brw_builder hbld = bld.exec_all().group(8, 0);
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
brw_reg *const components = new brw_reg[2 * m];

16
src/intel/compiler/brw_fs.h
View file

@ -138,9 +138,7 @@ struct brw_gs_compile
unsigned control_data_header_size_bits;
};
namespace brw {
class brw_builder;
}
struct brw_shader_stats {
const char *scheduler_mode;
@ -216,7 +214,7 @@ struct fs_thread_payload : public thread_payload {
struct cs_thread_payload : public thread_payload {
cs_thread_payload(const fs_visitor &v);
void load_subgroup_id(const brw::brw_builder &bld, brw_reg &dest) const;
void load_subgroup_id(const brw_builder &bld, brw_reg &dest) const;
brw_reg local_invocation_id[3];
@ -244,7 +242,7 @@ struct bs_thread_payload : public thread_payload {
brw_reg global_arg_ptr;
brw_reg local_arg_ptr;
void load_shader_type(const brw::brw_builder &bld, brw_reg &dest) const;
void load_shader_type(const brw_builder &bld, brw_reg &dest) const;
};
enum instruction_scheduler_mode {
@ -479,12 +477,12 @@ sample_mask_flag_subreg(const fs_visitor &s)
namespace brw {
brw_reg
fetch_payload_reg(const brw::brw_builder &bld, uint8_t regs[2],
fetch_payload_reg(const brw_builder &bld, uint8_t regs[2],
brw_reg_type type = BRW_TYPE_F,
unsigned n = 1);
brw_reg
fetch_barycentric_reg(const brw::brw_builder &bld, uint8_t regs[2]);
fetch_barycentric_reg(const brw_builder &bld, uint8_t regs[2]);
inline brw_reg
dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
@ -501,7 +499,7 @@ namespace brw {
lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
}
void shuffle_from_32bit_read(const brw::brw_builder &bld,
void shuffle_from_32bit_read(const brw_builder &bld,
const brw_reg &dst,
const brw_reg &src,
uint32_t first_component,
@ -515,8 +513,8 @@ uint32_t brw_fb_write_msg_control(const fs_inst *inst,
void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data);
brw_reg brw_sample_mask_reg(const brw::brw_builder &bld);
void brw_emit_predicate_on_sample_mask(const brw::brw_builder &bld, fs_inst *inst);
brw_reg brw_sample_mask_reg(const brw_builder &bld);
void brw_emit_predicate_on_sample_mask(const brw_builder &bld, fs_inst *inst);
int brw_get_subgroup_id_param_index(const intel_device_info *devinfo,
const brw_stage_prog_data *prog_data);

6
src/intel/compiler/brw_fs_nir.cpp
View file

@ -4822,7 +4822,7 @@ brw_reduce_op_for_nir_reduction_op(nir_op op)
}
static brw_reg
get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::brw_builder &bld,
get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw_builder &bld,
nir_intrinsic_instr *instr)
{
brw_reg surf_index = get_nir_src_imm(ntb, instr->src[0]);
@ -4833,7 +4833,7 @@ get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::brw_builder &bld
}
static brw_reg
get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw::brw_builder &bld,
get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw_builder &bld,
nir_intrinsic_instr *instr, bool *no_mask_handle = NULL)
{
/* SSBO stores are weird in that their index is in src[1] */
@ -4878,7 +4878,7 @@ get_nir_buffer_intrinsic_index(nir_to_brw_state &ntb, const brw::brw_builder &bl
*/
static brw_reg
swizzle_nir_scratch_addr(nir_to_brw_state &ntb,
const brw::brw_builder &bld,
const brw_builder &bld,
const nir_src &nir_addr_src,
bool in_dwords)
{

4
src/intel/compiler/brw_lower.cpp
View file

@ -606,7 +606,7 @@ brw_lower_alu_restrictions(fs_visitor &s)
assert(!inst->saturate);
assert(!inst->src[0].abs);
assert(!inst->src[0].negate);
const brw::brw_builder ibld(&s, block, inst);
const brw_builder ibld(&s, block, inst);
enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32);
@ -630,7 +630,7 @@ brw_lower_alu_restrictions(fs_visitor &s)
assert(!inst->src[0].abs && !inst->src[0].negate);
assert(!inst->src[1].abs && !inst->src[1].negate);
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
const brw::brw_builder ibld(&s, block, inst);
const brw_builder ibld(&s, block, inst);
enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32);