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Adapt FIFO code to deal with cases where the base GET/PUT value isn't 0.

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This commit is contained in:
Ben Skeggs 2006-11-17 04:50:37 +00:00
parent 9daf0812a1
commit 10172f7485
3 changed files with 18 additions and 11 deletions
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1
src/mesa/drivers/dri/nouveau/nouveau_context.h
View file

@ -43,6 +43,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
typedef struct nouveau_fifo_t{
u_int32_t* buffer;
u_int32_t* mmio;
u_int32_t put_base;
u_int32_t current;
u_int32_t put;
u_int32_t free;

16
src/mesa/drivers/dri/nouveau/nouveau_fifo.c
View file

@ -46,19 +46,19 @@ void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size)
#endif
u_int32_t fifo_get;
while(nmesa->fifo.free < size+1) {
fifo_get = NV_FIFO_READ(NV03_FIFO_REGS_DMAGET);
fifo_get = NV_FIFO_READ_GET();
if(nmesa->fifo.put >= fifo_get) {
nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
if(nmesa->fifo.free < size+1) {
OUT_RING(NV03_FIFO_CMD_REWIND); \
OUT_RING(NV03_FIFO_CMD_JUMP | nmesa->fifo.put_base);
if(fifo_get <= RING_SKIPS) {
if(nmesa->fifo.put <= RING_SKIPS) /* corner case - will be idle */
NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, RING_SKIPS + 1);
do { fifo_get = NV_FIFO_READ(NV03_FIFO_REGS_DMAGET); }
NV_FIFO_WRITE_PUT(RING_SKIPS + 1);
do { fifo_get = NV_FIFO_READ_GET(); }
while(fifo_get <= RING_SKIPS);
}
NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, RING_SKIPS);
NV_FIFO_WRITE_PUT(RING_SKIPS);
nmesa->fifo.current = nmesa->fifo.put = RING_SKIPS;
nmesa->fifo.free = fifo_get - (RING_SKIPS + 1);
}
@ -134,7 +134,11 @@ GLboolean nouveauFifoInit(nouveauContextPtr nmesa)
}
/* Setup our initial FIFO tracking params */
nmesa->fifo.free = fifo_init.cmdbuf_size >> 2;
nmesa->fifo.put_base = fifo_init.put_base;
nmesa->fifo.current = 0;
nmesa->fifo.put = 0;
nmesa->fifo.max = (fifo_init.cmdbuf_size >> 2) - 1;
nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
MESSAGE("Fifo init ok. Using context %d\n", fifo_init.channel);
return GL_TRUE;

12
src/mesa/drivers/dri/nouveau/nouveau_fifo.h
View file

@ -38,6 +38,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg))
#define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg)) = value;
#define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.put_base) >> 2)
#define NV_FIFO_WRITE_PUT(val) NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, ((val)<<2) + nmesa->fifo.put_base)
/*
* Ring/fifo interface
@ -107,11 +109,11 @@ extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
#define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current)
#define FIRE_RING() do { \
if (nmesa->fifo.current!=nmesa->fifo.put) {\
nmesa->fifo.put=nmesa->fifo.current;\
NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT,nmesa->fifo.put);\
}\
#define FIRE_RING() do { \
if (nmesa->fifo.current!=nmesa->fifo.put) { \
nmesa->fifo.put=nmesa->fifo.current; \
NV_FIFO_WRITE_PUT(nmesa->fifo.put); \
} \
}while(0)
extern void nouveauWaitForIdle(nouveauContextPtr nmesa);