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Add support for Radeon IGP chipsets, based off of mcgrof-radeon-igp-v3.diff
XFree86 bug: 314
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parent
283507075a
commit
10095c9024
5 changed files with 51 additions and 6 deletions
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@ -438,11 +438,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
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fprintf(stderr, "disabling 3D acceleration\n");
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FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
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}
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else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL")) {
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else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
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!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
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fprintf(stderr, "disabling TCL support\n");
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TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
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}
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else {
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if (rmesa->r200Screen->chipset & R200_CHIPSET_TCL) {
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if (tcl_mode >= DRI_CONF_TCL_VTXFMT && !getenv("R200_NO_VTXFMT")) {
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r200VtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
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}
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@ -89,6 +89,16 @@ static const GLuint __driNConfigOptions = 10;
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#define PCI_CHIP_R200_LY 0x4C59
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#define PCI_CHIP_R200_LZ 0x4C5A
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#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
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#define PCI_CHIP_RS100_4136 0x4136 /* IGP RS100, RS200, RS250 are not R200 */
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#define PCI_CHIP_RS200_4137 0x4137
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#define PCI_CHIP_RS250_4237 0x4237
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#define PCI_CHIP_RS100_4336 0x4336
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#define PCI_CHIP_RS200_4337 0x4337
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#define PCI_CHIP_RS250_4437 0x4437
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#define PCI_CHIP_RS300_5834 0x5834 /* All RS300's are R200 */
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#define PCI_CHIP_RS300_5835 0x5835
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#define PCI_CHIP_RS300_5836 0x5836
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#define PCI_CHIP_RS300_5837 0x5837
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#endif
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static r200ScreenPtr __r200Screen;
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@ -115,6 +125,7 @@ r200CreateScreen( __DRIscreenPrivate *sPriv )
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return NULL;
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}
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screen->chipset = 0;
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switch ( dri_priv->deviceID ) {
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case PCI_CHIP_R200_QD:
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case PCI_CHIP_R200_QE:
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@ -126,11 +137,24 @@ r200CreateScreen( __DRIscreenPrivate *sPriv )
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case PCI_CHIP_R200_LW:
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case PCI_CHIP_R200_LY:
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case PCI_CHIP_R200_LZ:
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case PCI_CHIP_RS100_4136:
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case PCI_CHIP_RS200_4137:
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case PCI_CHIP_RS250_4237:
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case PCI_CHIP_RS100_4336:
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case PCI_CHIP_RS200_4337:
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case PCI_CHIP_RS250_4437:
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__driUtilMessage("r200CreateScreen(): Device isn't an r200!\n");
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FREE( screen );
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return NULL;
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return NULL;
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case PCI_CHIP_RS300_5834:
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case PCI_CHIP_RS300_5835:
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case PCI_CHIP_RS300_5836:
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case PCI_CHIP_RS300_5837:
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break;
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default:
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screen->chipset = R200_CHIPSET_R200;
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screen->chipset |= R200_CHIPSET_TCL;
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break;
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}
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@ -50,8 +50,9 @@ typedef struct {
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drmAddress map; /* Mapping of the DRM region */
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} r200RegionRec, *r200RegionPtr;
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#define R200_CHIPSET_R200 1
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#define R200_CHIPSET_MOBILITY 2
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/* chipset features */
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#define R200_CHIPSET_TCL (1 << 0)
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#define R200_NR_TEX_HEAPS 2
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@ -461,6 +461,12 @@ void r200InitState( r200ContextPtr rmesa )
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#else
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R200_VC_NO_SWAP;
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#endif
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if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
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/* Bypass TCL */
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rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
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}
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rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 0x100010;
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rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
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(0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
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@ -92,6 +92,13 @@ static const GLuint __driNConfigOptions = 10;
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#define PCI_CHIP_RADEON_LZ 0x4C5A
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#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
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/* IGP Chipsets */
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#define PCI_CHIP_RS100_4136 0x4136
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#define PCI_CHIP_RS200_4137 0x4137
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#define PCI_CHIP_RS250_4237 0x4237
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#define PCI_CHIP_RS100_4336 0x4336
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#define PCI_CHIP_RS200_4337 0x4337
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#define PCI_CHIP_RS250_4437 0x4437
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#endif
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static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
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@ -224,6 +231,12 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
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case PCI_CHIP_RADEON_QZ:
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case PCI_CHIP_RADEON_LY:
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case PCI_CHIP_RADEON_LZ:
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case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
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case PCI_CHIP_RS200_4137:
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case PCI_CHIP_RS250_4237:
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case PCI_CHIP_RS100_4336:
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case PCI_CHIP_RS200_4337:
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case PCI_CHIP_RS250_4437:
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break;
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}
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