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radv: add support for dynamic line rasterization mode

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19924>
This commit is contained in:
Samuel Pitoiset 2022-11-22 09:07:25 +01:00
parent f992e663c7
commit 1009276312
3 changed files with 52 additions and 29 deletions
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40
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -136,6 +136,7 @@ const struct radv_dynamic_state default_dynamic_state = {
.color_write_mask = 0u,
.color_blend_enable = 0u,
.rasterization_samples = VK_SAMPLE_COUNT_1_BIT,
.line_rasterization_mode = VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT,
};
static void
@ -297,6 +298,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy
RADV_CMP_COPY(rasterization_samples, RADV_DYNAMIC_RASTERIZATION_SAMPLES);
RADV_CMP_COPY(line_rasterization_mode, RADV_DYNAMIC_LINE_RASTERIZATION_MODE);
#undef RADV_CMP_COPY
cmd_buffer->state.dirty |= dest_mask;
@ -963,7 +966,17 @@ radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
if (pipeline->uses_bresenham_lines) {
if (d->line_rasterization_mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT &&
radv_rast_prim_is_line(pipeline->rast_prim)) {
/* From the Vulkan spec 1.3.221:
*
* "When Bresenham lines are being rasterized, sample locations may all be treated as being at
* the pixel center (this may affect attribute and depth interpolation)."
*
* "One consequence of this is that Bresenham lines cover the same pixels regardless of the
* number of rasterization samples, and cover all samples in those pixels (unless masked out
* or killed)."
*/
return 1;
}
@ -1937,9 +1950,9 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable ||
cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
cmd_buffer->state.emitted_graphics_pipeline->uses_bresenham_lines != pipeline->uses_bresenham_lines ||
cmd_buffer->state.emitted_graphics_pipeline->pa_sc_mode_cntl_1 != pipeline->pa_sc_mode_cntl_1 ||
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control)
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
@ -4218,13 +4231,15 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip
if (states & RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE)
radv_emit_color_blend_enable(cmd_buffer);
if (states & RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES)
if (states & (RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES |
RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE))
radv_emit_rasterization_samples(cmd_buffer);
if (states & (RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE |
RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS |
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES))
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES |
RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE))
radv_emit_msaa_state(cmd_buffer);
cmd_buffer->state.dirty &= ~states;
@ -6868,6 +6883,18 @@ radv_CmdSetRasterizationSamplesEXT(VkCommandBuffer commandBuffer,
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetLineRasterizationModeEXT(VkCommandBuffer commandBuffer,
VkLineRasterizationModeEXT lineRasterizationMode)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
state->dynamic.line_rasterization_mode = lineRasterizationMode;
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE;
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount,
const VkCommandBuffer *pCmdBuffers)
@ -8417,7 +8444,8 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
radv_emit_ngg_culling_state(cmd_buffer, info);
if ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK |
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES)) ||
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES |
RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE)) ||
cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline)
radv_emit_binning_state(cmd_buffer, cmd_buffer->state.graphics_pipeline);

20
src/amd/vulkan/radv_pipeline.c
View file

@ -1089,20 +1089,6 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline,
S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
if (state->rs->line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT &&
radv_rast_prim_is_line(rast_prim)) {
/* From the Vulkan spec 1.3.221:
*
* "When Bresenham lines are being rasterized, sample locations may all be treated as being at
* the pixel center (this may affect attribute and depth interpolation)."
*
* "One consequence of this is that Bresenham lines cover the same pixels regardless of the
* number of rasterization samples, and cover all samples in those pixels (unless masked out
* or killed)."
*/
pipeline->uses_bresenham_lines = true;
}
}
static void
@ -1267,6 +1253,8 @@ radv_dynamic_state_mask(VkDynamicState state)
return RADV_DYNAMIC_COLOR_BLEND_ENABLE;
case VK_DYNAMIC_STATE_RASTERIZATION_SAMPLES_EXT:
return RADV_DYNAMIC_RASTERIZATION_SAMPLES;
case VK_DYNAMIC_STATE_LINE_RASTERIZATION_MODE_EXT:
return RADV_DYNAMIC_LINE_RASTERIZATION_MODE;
default:
unreachable("Unhandled dynamic state");
}
@ -1868,6 +1856,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
dynamic->rasterization_samples = state->ms->rasterization_samples;
}
if (states & RADV_DYNAMIC_LINE_RASTERIZATION_MODE) {
dynamic->line_rasterization_mode = state->rs->line.mode;
}
pipeline->dynamic_state.mask = states;
}

21
src/amd/vulkan/radv_private.h
View file

@ -1137,7 +1137,8 @@ enum radv_dynamic_state_bits {
RADV_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41,
RADV_DYNAMIC_COLOR_BLEND_ENABLE = 1ull << 42,
RADV_DYNAMIC_RASTERIZATION_SAMPLES = 1ull << 43,
RADV_DYNAMIC_ALL = (1ull << 44) - 1,
RADV_DYNAMIC_LINE_RASTERIZATION_MODE = 1ull << 44,
RADV_DYNAMIC_ALL = (1ull << 45) - 1,
};
enum radv_cmd_dirty_bits {
@ -1187,13 +1188,14 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41,
RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE = 1ull << 42,
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES = 1ull << 43,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 44) - 1,
RADV_CMD_DIRTY_PIPELINE = 1ull << 44,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 45,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 46,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 47,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 48,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 49,
RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE = 1ull << 44,
RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 45) - 1,
RADV_CMD_DIRTY_PIPELINE = 1ull << 45,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 46,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 47,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 48,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 49,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 50,
};
enum radv_cmd_flush_bits {
@ -1419,6 +1421,8 @@ struct radv_dynamic_state {
uint32_t color_blend_enable;
VkSampleCountFlagBits rasterization_samples;
VkLineRasterizationModeEXT line_rasterization_mode;
};
extern const struct radv_dynamic_state default_dynamic_state;
@ -2133,7 +2137,6 @@ struct radv_graphics_pipeline {
bool use_per_attribute_vb_descs;
bool can_use_simple_input;
bool uses_user_sample_locations;
bool uses_bresenham_lines;
/* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
bool force_vrs_per_vertex;