From 0fc93928f19aa0ad4eb81dab2ddb97a1d602685e Mon Sep 17 00:00:00 2001
From: Jordan Justen <jordan.l.justen@intel.com>
Date: Thu, 6 Jan 2022 13:33:07 -0800
Subject: [PATCH] isl: Don't enable HDC:L1 caches on DG2

The MOCS entry used for this on Tigerlake doesn't exist on DG2.

Ref: aca31baafc0 ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14467>
---
 src/intel/isl/isl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index cc775ea5c3f..0c70ce680e6 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -170,7 +170,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
    if (external)
       return dev->mocs.external;
 
-   if (dev->info->ver >= 12 && dev->info->platform != INTEL_PLATFORM_DG1) {
+   if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) {
       if (usage & ISL_SURF_USAGE_STAGING_BIT)
          return dev->mocs.internal;